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DATA SHEET
MOS INTEGRATED CIRCUIT
PD161623
528 OUTPUT TFT-LCD SOURCE DRIVER WITH RAM
DESCRIPTION
The PD161623 is a TFT-LCD source driver that includes display RAM. This driver has 528 outputs, a display RAM capacity of 760,320 bits (176 pixels x 18 bits x 240 lines) and, can provide a 262,144-color display.
FEATURES
* TFT-LCD driver with on-chip display RAM * I/O circuit power supply voltage: 1.7 to 3.6 V * Logic power supply voltage: 2.5 to 3.6 V * Driver power supply voltage: 4.3 to 5.5 V * Display RAM: 176 x 18 x 240 bits * Driver outputs: 528 output * CPU interface: Serial, 18-bit/16-bit parallel interface selectable * Colors: 262,144 colors/pixel * On-chip VCOM generator * On-chip timing generator * On-chip oscillator
ORDERING INFORMATION
Part Number Package Chip
PD161623P
Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum on product quality, so please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S15817EJ2V0DS00 (2nd edition) Date Published July 2002 NS CP(K) Printed in Japan
The mark 5 shows major revised points.
(c)
2001
PD161623
1. BLOCK DIAGRAM
VSS VDD1(MODE) VDD2(MODE) VSS(MODE) V0 to V5 VRH
VDD1 VDD2
Y1 Y2 Y3 Y4
Y527 Y528
VRL1 VRL2
LCD drive circuit
Gray scale generator
CVPH CVPL CVNH CVNL
Decoder
Level shifter (2.5 V Display data latch
5 V)
LCD timing control
Display data RAM (176 x 18 x 240 bits)
Calibrator
Oscillator RAM controller BGR
OSCIN OSCOUT OSCSEL
BGRIN Internal timing generator Command decoder
D/A converter
Address decoder / controller
Data register VCOM generator
DAC0 to DAC7 VCOMR FBRSEL
I/O buffer
Gate control
PS control
PSX1 SI SCL TOUT0 to TOUT17 TOSCO TOSCI TOSCSELI TOSCSELO TSTRTST TSTVIHL TBSEL1 TBSEL2 TBGR PSX0 /CS /RESET /RD(E) /WR(R, /W) C86 DTX D0 to D17 RS OP0 to OP7 CSTB
Remark
/xxx indicates active low signal.
2
Data Sheet S15817EJ2V0DS
VCOM VCOUT1 VCOUT2
LPMP DCON VCD11 VCD12 VCD2 VCE RGONP
GSTB GCLK
GOE1
GOE2
PD161623
2. PIN CONFIGURATION (PAD LAYOUT)
Chip size: 3.75 x 23.00 mm TYP. Bump size (output): 35 x 94 m TYP.
2 2
Bump size (input & dummy): 80 x 86 m TYP.
2
Alignment mark (Mark center, unit: m)
X M1 M2 -1690 -1690 Y 11315 -11315
737
734 733
Alignment mark reference (unit: m)
1
72
72 60 204 72
72
204
60
Y(+ X(+
130 m
185 186 189
190
Data Sheet S15817EJ2V0DS
41.5 m
41.5 m
3
PD161623
Table 2-1. Pad Layout (1/4)
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Pad Name DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY TOUT17 TOUT16 TOUT15 TOUT14 TOUT13 TOUT12 TOUT11 TOUT10 TOUT9 TOUT8 TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0 VSS(MODE) TSTVIHL TSTRTST TOSCSELO TOSCSELI TOSCI TOSCO VDD2(MODE) OSCSEL VSS(MODE) OSCOUT VSS(MODE) OSCIN VSS(MODE) CSTB D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VSS(MODE) /CS /RESET Pad Type B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B Pad Layout [m] X -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 Y 11000.00 10880.00 10760.00 10640.00 10520.00 10400.00 10280.00 10160.00 10040.00 9920.00 9800.00 9680.00 9560.00 9440.00 9320.00 9200.00 9080.00 8960.00 8840.00 8720.00 8600.00 8480.00 8360.00 8240.00 8120.00 8000.00 7880.00 7760.00 7640.00 7520.00 7400.00 7280.00 7160.00 7040.00 6920.00 6800.00 6680.00 6560.00 6440.00 6320.00 6200.00 6080.00 5960.00 5840.00 5720.00 5600.00 5480.00 5360.00 5240.00 5120.00 5000.00 4880.00 4760.00 4640.00 4520.00 4400.00 4280.00 4160.00 4040.00 3920.00 3800.00 3680.00 3560.00 3440.00 3320.00 3200.00 3080.00 2960.00 2840.00 2720.00 Pad No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Pad Name RS /WR (R, /W) /RD (E) VSS(MODE) SI SCL VDD1 PSX1 VSS(MODE) PSX0 VDD1(MODE) C86 VSS(MODE) DTX VDD1(MODE) VCE VCD2 VCD12 VCD11 LPMP RGONP DCON VCOUT2 VSS VDD1 VDD2 VSS VSS CVNL CVNH CVPL CVPH VS VS VSS VCOUT1 VCOUT1 VDD2 VDD2 VCOM DUMMY DUMMY VSS(MODE) VCOMR BGRIN VDD2(MODE) FBRSEL VSS(MODE) VRH V0 V1 V2 V3 V4 V5 VRL1 VRL2 VSS(MODE) TBSEL1 TBSEL2 TBGR DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 VSS(MODE) Pad Type B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B Pad Layout [m] X -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 Y 2600.00 2480.00 2360.00 2240.00 2120.00 2000.00 1880.00 1760.00 1640.00 1520.00 1400.00 1280.00 1160.00 1040.00 920.00 800.00 680.00 560.00 440.00 320.00 200.00 80.00 -40.00 -160.00 -280.00 -400.00 -520.00 -640.00 -760.00 -880.00 -1000.00 -1120.00 -1240.00 -1360.00 -1480.00 -1600.00 -1720.00 -1840.00 -1960.00 -2080.00 -2200.00 -2320.00 -2440.00 -2560.00 -2680.00 -2800.00 -2920.00 -3040.00 -3160.00 -3280.00 -3400.00 -3520.00 -3640.00 -3760.00 -3880.00 -4000.00 -4120.00 -4240.00 -4360.00 -4480.00 -4600.00 -4720.00 -4840.00 -4960.00 -5080.00 -5200.00 -5320.00 -5440.00 -5560.00 -5680.00 Pad No. 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 Pad Name OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 GSTB GCLK GOE1 GOE2 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY Y528 Y527 Y526 Y525 Y524 Y523 Y522 Y521 Y520 Y519 Y518 Y517 Y516 Y515 Y514 Y513 Y512 Y511 Pad Type B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A A A A A A Pad Layout [m] X -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1749.00 -1350.00 -450.00 450.00 1350.00 1745.00 1745.00 1745.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 Y -5800.00 -5920.00 -6040.00 -6160.00 -6280.00 -6400.00 -6520.00 -6640.00 -6760.00 -6880.00 -7000.00 -7120.00 -7240.00 -7360.00 -7480.00 -7600.00 -7720.00 -7840.00 -7960.00 -8080.00 -8200.00 -8320.00 -8440.00 -8560.00 -8680.00 -8800.00 -8920.00 -9040.00 -9160.00 -9280.00 -9400.00 -9520.00 -9640.00 -9760.00 -9880.00 -10000.00 -10120.00 -10240.00 -10360.00 -10480.00 -10600.00 -10720.00 -10840.00 -10960.00 -11080.00 -11374.00 -11374.00 -11374.00 -11374.00 -11302.50 -11252.50 -11201.50 -11140.50 -11099.00 -11057.50 -11016.00 -10974.50 -10933.00 -10891.50 -10850.00 -10808.50 -10767.00 -10725.50 -10684.00 -10642.50 -10601.00 -10559.50 -10518.00 -10476.50 -10435.00
4
Data Sheet S15817EJ2V0DS
PD161623
Table 2-1. Pad Layout (2/4)
Pad No. 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 Pad Name Y510 Y509 Y508 Y507 Y506 Y505 Y504 Y503 Y502 Y501 Y500 Y499 Y498 Y497 Y496 Y495 Y494 Y493 Y492 Y491 Y490 Y489 Y488 Y487 Y486 Y485 Y484 Y483 Y482 Y481 Y480 Y479 Y478 Y477 Y476 Y475 Y474 Y473 Y472 Y471 Y470 Y469 Y468 Y467 Y466 Y465 Y464 Y463 Y462 Y461 Y460 Y459 Y458 Y457 Y456 Y455 Y454 Y453 Y452 Y451 Y450 Y449 Y448 Y447 Y446 Y445 Y444 Y443 Y442 Y441 Pad Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad Layout [m] X 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 Y -10393.50 -10352.00 -10310.50 -10269.00 -10227.50 -10186.00 -10144.50 -10103.00 -10061.50 -10020.00 -9978.50 -9937.00 -9895.50 -9854.00 -9812.50 -9771.00 -9729.50 -9688.00 -9646.50 -9605.00 -9563.50 -9522.00 -9480.50 -9439.00 -9397.50 -9356.00 -9314.50 -9273.00 -9231.50 -9190.00 -9148.50 -9107.00 -9065.50 -9024.00 -8982.50 -8941.00 -8899.50 -8858.00 -8816.50 -8775.00 -8733.50 -8692.00 -8650.50 -8609.00 -8567.50 -8526.00 -8484.50 -8443.00 -8401.50 -8360.00 -8318.50 -8277.00 -8235.50 -8194.00 -8152.50 -8111.00 -8069.50 -8028.00 -7986.50 -7945.00 -7903.50 -7862.00 -7820.50 -7779.00 -7737.50 -7696.00 -7654.50 -7613.00 -7571.50 -7530.00 Pad No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 Pad Name Y440 Y439 Y438 Y437 Y436 Y435 Y434 Y433 Y432 Y431 Y430 Y429 Y428 Y427 Y426 Y425 Y424 Y423 Y422 Y421 Y420 Y419 Y418 Y417 Y416 Y415 Y414 Y413 Y412 Y411 Y410 Y409 Y408 Y407 Y406 Y405 Y404 Y403 Y402 Y401 Y400 Y399 Y398 Y397 Y396 Y395 Y394 Y393 Y392 Y391 Y390 Y389 Y388 Y387 Y386 Y385 Y384 Y383 Y382 Y381 Y380 Y379 Y378 Y377 Y376 Y375 Y374 Y373 Y372 Y371 Pad Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad Layout [m] X 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 Y -7488.50 -7447.00 -7405.50 -7364.00 -7322.50 -7281.00 -7239.50 -7198.00 -7156.50 -7115.00 -7073.50 -7032.00 -6990.50 -6949.00 -6907.50 -6866.00 -6824.50 -6783.00 -6741.50 -6700.00 -6658.50 -6617.00 -6575.50 -6534.00 -6492.50 -6451.00 -6409.50 -6368.00 -6326.50 -6285.00 -6243.50 -6202.00 -6160.50 -6119.00 -6077.50 -6036.00 -5994.50 -5953.00 -5911.50 -5870.00 -5828.50 -5787.00 -5745.50 -5704.00 -5662.50 -5621.00 -5579.50 -5538.00 -5496.50 -5455.00 -5413.50 -5372.00 -5330.50 -5289.00 -5247.50 -5206.00 -5164.50 -5123.00 -5081.50 -5040.00 -4998.50 -4957.00 -4915.50 -4874.00 -4832.50 -4791.00 -4749.50 -4708.00 -4666.50 -4625.00 Pad No. 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 Pad Name Y370 Y369 Y368 Y367 Y366 Y365 Y364 Y363 Y362 Y361 Y360 Y359 Y358 Y357 Y356 Y355 Y354 Y353 Y352 Y351 Y350 Y349 Y348 Y347 Y346 Y345 Y344 Y343 Y342 Y341 Y340 Y339 Y338 Y337 Y336 Y335 Y334 Y333 Y332 Y331 Y330 Y329 Y328 Y327 Y326 Y325 Y324 Y323 Y322 Y321 Y320 Y319 Y318 Y317 Y316 Y315 Y314 Y313 Y312 Y311 Y310 Y309 Y308 Y307 Y306 Y305 Y304 Y303 Y302 Y301 Pad Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad Layout [m] X 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 Y -4583.50 -4542.00 -4500.50 -4459.00 -4417.50 -4376.00 -4334.50 -4293.00 -4251.50 -4210.00 -4168.50 -4127.00 -4085.50 -4044.00 -4002.50 -3961.00 -3919.50 -3878.00 -3836.50 -3795.00 -3753.50 -3712.00 -3670.50 -3629.00 -3587.50 -3546.00 -3504.50 -3463.00 -3421.50 -3380.00 -3338.50 -3297.00 -3255.50 -3214.00 -3172.50 -3131.00 -3089.50 -3048.00 -3006.50 -2965.00 -2923.50 -2882.00 -2840.50 -2799.00 -2757.50 -2716.00 -2674.50 -2633.00 -2591.50 -2550.00 -2508.50 -2467.00 -2425.50 -2384.00 -2342.50 -2301.00 -2259.50 -2218.00 -2176.50 -2135.00 -2093.50 -2052.00 -2010.50 -1969.00 -1927.50 -1886.00 -1844.50 -1803.00 -1761.50 -1720.00
Data Sheet S15817EJ2V0DS
5
PD161623
Table 2-1. Pad Layout (3/4)
Pad No. 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 Pad Name Y300 Y299 Y298 Y297 Y296 Y295 Y294 Y293 Y292 Y291 Y290 Y289 Y288 Y287 Y286 Y285 Y284 Y283 Y282 Y281 Y280 Y279 Y278 Y277 Y276 Y275 Y274 Y273 Y272 Y271 Y270 Y269 Y268 Y267 Y266 Y265 Y264 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY Y263 Y262 Y261 Y260 Y259 Y258 Y257 Y256 Y255 Y254 Y253 Y252 Y251 Y250 Y249 Y248 Y247 Y246 Y245 Y244 Y243 Y242 Y241 Pad Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad Layout [m] X 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 Y -1678.50 -1637.00 -1595.50 -1554.00 -1512.50 -1471.00 -1429.50 -1388.00 -1346.50 -1305.00 -1263.50 -1222.00 -1180.50 -1139.00 -1097.50 -1056.00 -1014.50 -973.00 -931.50 -890.00 -848.50 -807.00 -765.50 -724.00 -682.50 -641.00 -599.50 -558.00 -516.50 -475.00 -433.50 -392.00 -350.50 -309.00 -267.50 -226.00 -184.50 -143.00 -101.50 -60.00 -18.50 23.00 64.50 106.00 147.50 189.00 230.50 272.00 313.50 355.00 396.50 438.00 479.50 521.00 562.50 604.00 645.50 687.00 728.50 770.00 811.50 853.00 894.50 936.00 977.50 1019.00 1060.50 1102.00 1143.50 1185.00 Pad No. 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 Pad Name Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233 Y232 Y231 Y230 Y229 Y228 Y227 Y226 Y225 Y224 Y223 Y222 Y221 Y220 Y219 Y218 Y217 Y216 Y215 Y214 Y213 Y212 Y211 Y210 Y209 Y208 Y207 Y206 Y205 Y204 Y203 Y202 Y201 Y200 Y199 Y198 Y197 Y196 Y195 Y194 Y193 Y192 Y191 Y190 Y189 Y188 Y187 Y186 Y185 Y184 Y183 Y182 Y181 Y180 Y179 Y178 Y177 Y176 Y175 Y174 Y173 Y172 Y171 Pad Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad Layout [m] X 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 Y 1226.50 1268.00 1309.50 1351.00 1392.50 1434.00 1475.50 1517.00 1558.50 1600.00 1641.50 1683.00 1724.50 1766.00 1807.50 1849.00 1890.50 1932.00 1973.50 2015.00 2056.50 2098.00 2139.50 2181.00 2222.50 2264.00 2305.50 2347.00 2388.50 2430.00 2471.50 2513.00 2554.50 2596.00 2637.50 2679.00 2720.50 2762.00 2803.50 2845.00 2886.50 2928.00 2969.50 3011.00 3052.50 3094.00 3135.50 3177.00 3218.50 3260.00 3301.50 3343.00 3384.50 3426.00 3467.50 3509.00 3550.50 3592.00 3633.50 3675.00 3716.50 3758.00 3799.50 3841.00 3882.50 3924.00 3965.50 4007.00 4048.50 4090.00 Pad No. 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 Pad Name Y170 Y169 Y168 Y167 Y166 Y165 Y164 Y163 Y162 Y161 Y160 Y159 Y158 Y157 Y156 Y155 Y154 Y153 Y152 Y151 Y150 Y149 Y148 Y147 Y146 Y145 Y144 Y143 Y142 Y141 Y140 Y139 Y138 Y137 Y136 Y135 Y134 Y133 Y132 Y131 Y130 Y129 Y128 Y127 Y126 Y125 Y124 Y123 Y122 Y121 Y120 Y119 Y118 Y117 Y116 Y115 Y114 Y113 Y112 Y111 Y110 Y109 Y108 Y107 Y106 Y105 Y104 Y103 Y102 Y101 Pad Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad Layout [m] X 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 Y 4131.50 4173.00 4214.50 4256.00 4297.50 4339.00 4380.50 4422.00 4463.50 4505.00 4546.50 4588.00 4629.50 4671.00 4712.50 4754.00 4795.50 4837.00 4878.50 4920.00 4961.50 5003.00 5044.50 5086.00 5127.50 5169.00 5210.50 5252.00 5293.50 5335.00 5376.50 5418.00 5459.50 5501.00 5542.50 5584.00 5625.50 5667.00 5708.50 5750.00 5791.50 5833.00 5874.50 5916.00 5957.50 5999.00 6040.50 6082.00 6123.50 6165.00 6206.50 6248.00 6289.50 6331.00 6372.50 6414.00 6455.50 6497.00 6538.50 6580.00 6621.50 6663.00 6704.50 6746.00 6787.50 6829.00 6870.50 6912.00 6953.50 6995.00
6
Data Sheet S15817EJ2V0DS
PD161623
Table 2-1. Pad Layout (4/4)
Pad No. 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 Pad Name Y100 Y99 Y98 Y97 Y96 Y95 Y94 Y93 Y92 Y91 Y90 Y89 Y88 Y87 Y86 Y85 Y84 Y83 Y82 Y81 Y80 Y79 Y78 Y77 Y76 Y75 Y74 Y73 Y72 Y71 Y70 Y69 Y68 Y67 Y66 Y65 Y64 Y63 Y62 Y61 Y60 Y59 Y58 Y57 Y56 Y55 Y54 Y53 Y52 Y51 Y50 Y49 Y48 Y47 Y46 Y45 Y44 Y43 Y42 Y41 Y40 Y39 Y38 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Pad Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad Layout [m] X 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 Y 7036.50 7078.00 7119.50 7161.00 7202.50 7244.00 7285.50 7327.00 7368.50 7410.00 7451.50 7493.00 7534.50 7576.00 7617.50 7659.00 7700.50 7742.00 7783.50 7825.00 7866.50 7908.00 7949.50 7991.00 8032.50 8074.00 8115.50 8157.00 8198.50 8240.00 8281.50 8323.00 8364.50 8406.00 8447.50 8489.00 8530.50 8572.00 8613.50 8655.00 8696.50 8738.00 8779.50 8821.00 8862.50 8904.00 8945.50 8987.00 9028.50 9070.00 9111.50 9153.00 9194.50 9236.00 9277.50 9319.00 9360.50 9402.00 9443.50 9485.00 9526.50 9568.00 9609.50 9651.00 9692.50 9734.00 9775.50 9817.00 9858.50 9900.00 Pad No. 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 Pad Name Y30 Y29 Y28 Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY Pad Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B B B Pad Layout [m] X 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1615.00 1745.00 1745.00 1745.00 1340.00 440.00 -460.00 -1360.00 Y 9941.50 9983.00 10024.50 10066.00 10107.50 10149.00 10190.50 10232.00 10273.50 10315.00 10356.50 10398.00 10439.50 10481.00 10522.50 10564.00 10605.50 10647.00 10688.50 10730.00 10771.50 10813.00 10854.50 10896.00 10937.50 10979.00 11020.50 11062.00 11103.50 11145.00 11206.50 11257.50 11307.50 11374.00 11374.00 11374.00 11374.00
Data Sheet S15817EJ2V0DS
7
PD161623
3. PIN FUNCTIONS
3.1 Power Supply System Pins
Symbol VDD1 VDD2 VS VSS V0 to V5 VRH VRL1, VRL2 Pin Name Logic power supply I/O power supply Driver power supply Ground Power supply for -curve correction Pad No. 77, 95 96, 108, 109 103, 104
94, 97, 98, 105
I/O - - - - - Power supply pin for logic circuit Power supply pin for I/O buffer Power supply pin for driver circuit
Function
Ground pin for logic and driver circuits The PD161623 includes power supplies and registers for the -curve, so if the characteristics of the -curve and LCD panel in the PD161623 match, leave V0 to V5, VRH, VRL1, VRL2 open. If some kind of correction is required, adjust the -curve by connecting registers between the V0 to V5, VRH, VRL1, VRL2 pins (see 5.9 -Curve Correction Power Supply Circuit). Pull-up power supply pin for mode setting Pull-down power supply pin for mode setting Ground pin for mode setting
120 to 125, 119, 126, 127
VDD1 (MODE) VDD2 (MODE) VSS (MODE)
Mode setting pull-up power supply
81, 85
- - -
Mode setting pull-down 42, 116 power supply Mode setting ground
35, 44, 46, 48, 68, 74, 79, 83, 113, 118, 128, 140
3.2 Logic System Pins
Symbol PSX0 Pin Name Pad No. CPU interface selection 80 I/O Function Input This pin is used to select the CPU interface mode. PSX0 H L /CS /RESET Chip select Reset 69 70 CPU Interface Mode 18-bit parallel interface 16-bit parallel interface
(1/2)
Input This pin is used for chip select signals. When /CS = L, the chip is active and can perform data input/output operations including command and data I/O. Input When /RESET is L, an internal reset is performed. The reset operation is executed at the /RESET signal level. Be sure to perform reset via this pin at power application.
/RD (E)
Read (Enable)
73
Input When i80 series parallel data transfer (/RD) has been selected, the signal at this pin is used to enable read operations. Data is output to the data bus only when this pin is low. When M68 series parallel data transfer (E) has been selected, the signal at this pin is used to enable read/write operations.
/WR (R, /W)
Write (Read/write)
72
Input When i80 series parallel data transfer (/WR) has been selected, the signal at this pin is used to enable write operations. Data is written at the rising edge of this signal. When M68 series parallel data transfer (R, /W) and serial data has been selected, this pin is used to determine the direction of data transfer. L: Write H: Read
C86
Select interface
82
Input This pin is used to switch between interface modes (i80 series CPU or M68 series CPU). L: Selects i80 series CPU mode H: Selects M68 series CPU mode
8
Data Sheet S15817EJ2V0DS
PD161623
(2/2)
Symbol D0 to D17 RS Pin Name Data bus Data/command selection Pad No. 67 to 50 71 I/O I/O Input Function These pins comprise 18-bit bi-directional data. When the chip is not selected, D0 to D17 are in high impedance mode. When parallel data transfer has been selected, this pin is usually connected to the least significant bit of the standard CPU address bus and is used to distinguish between data from display data and commands. RS = H: Indicates that data from D0 to D17 is display data. RS = L: Indicates that data from D0 to D17 is commands. DTX Data major select 84 Input When parallel data transfer has been selected, this pin is selected data major selection that inputs display data through serial interface. DTX = H: 1-pixel/18-bit mode DTX = L: 1-pixel/16-bit mode OSCSEL Oscillation signal selection 43 Input This pin is for oscillation signal selection. When is used external resistance connected oscillation circuit, this pin sets H. When in used CR internal oscillation circuit, this pin sets L. OSCSEL = H: External resistance connected oscillation circuit select OSCSEL = L: CR internal oscillation circuit select OSCIN Oscillation signal 47 Input This pin is for oscillation signal input. OSCSEL = H: Connect 42 k resistance between OSCIN and OSCOUT. (240 line, in case of NGO = 0) OSCSEL = L: Leave it open. OSCOUT Oscillation signal 45 Output This pin is for oscillation signal input. OSCSEL = H: Connect 42 k resistance between OSCIN and OSCOUT. (240 line, in case of NGO = 0) OSCSEL = L: Leave it open. CSTB OP0 to OP7 GSTB logic signal Output port 49 141 to 148 Output Output This pin outputs STB signal for gate driver leveled by interface power supply voltage (VDD1). This output signal is reverse signal of GSTB. This is a general-purpose output port. The status of these pins (H or L) can be write via a command. Leave open when in unused.
3.3 Gate Driver IC Control Pins
Symbol GOE1 Pin Name OE1 output for gate driver Pad No. 151 I/O Function Output This pin is an output pin for the low power mode (for the OE1). Connect to the OE1 pin of the gate driver. Timing signal for output, refer to 5.4 Display Timing Generator. GOE2 OE2 output for gate driver 152 Output This pin is the OE2 output for the gate driver. Connect to the OE2 pin of the gate driver. Timing signal for output, refer to 5.4 Display Timing Generator. GSTB STB output for gate driver 149 Output This pin is the STB output for the gate driver. Connect to the STVR or STVL pin of the gate driver. Timing signal for output, refer to 5.4 Display Timing Generator. GCLK CLK output for gate driver 150 Output This pin is the CLK output for the gate driver. Connect to the CLK pin of the gate driver.
Data Sheet S15817EJ2V0DS
9
PD161623
3.4 Power Supply Control Pins
Symbol LPMP Pin Name Low power mode signal Pad No. 90 I/O Function This pin connects to LPM pin of power supply IC. DCON DC/DC converter control 92 Output DC/DC converter ON/OFF signal pin for power supply IC. This pin connects DCON pin of power supply IC. RGONP Regulator control 91 Output Regulator ON/OFF control signal pin for power supply IC. This pin connects to RGONP pin of power supply IC. VCD11, VCD12 VDD1 booster selection 89, 88 Output Control signal to select x4/x5/x6/x7 booster of power supply IC for VDD1. Connect to the VCD11 and VCD12 pins of the power supply IC. VCD2 VDD2 booster selection 87 Output Control signal to select x2/x3 booster of power supply IC for VDD2. Connect to the VCD2 pin of the power supply IC. VCE VO level selection 86 Output Signal for selecting the level of the power supply IC booster voltage, to be used for the maximum voltage of VO. Selects that the booster voltage level is either the same level as VDD1 or a multiple of minus 1. Connect to the VCE pin of the power supply IC. Output Low power mode control signal output pin (for power supply IC).
3.5 Driver-Related Pins
Symbol Y1 to Y528 Pin Name Source output Pad No.
730 to 468, 457 to 193
(1/2)
I/O Function Output These pins are source output pins.
VCOM VCOUT1
COM adjustment
110
Output This pin is the common adjustment output pin. Output This pin is the center rectangle signal output (Vp-p) for common modulation between 0 V and VS. Output This pin is the center rectangle signal output (Vp-p) for common modulation between 0 V and VDD2.
Center rectangle signal 106, 107 output
VCOUT2
Center rectangle signal 93 output
BGRIN
External-power supply connect
115
Input
This is an external-power supply input pin for VCOM. This pin is valid when BGRS (power supply control register 1: R25) = 1. In this case, the reference voltage of the amplifier for setting the common waveform center value is input from outside the PD161623. When BGRS = 0, the PD161623 internal voltage is set as the reference voltage of the amplifier for setting the common waveform center value. In this case, leave it open.
VCOMR
VCOM setting register connection
114
Input
This pin connects an external feedback resistor for setting VCOM. This pin is valid when FBRSEL = L. In this case, connect a feedback resistor between the VCOM pin and GND. When FBRSEL = H, the amplifier for setting the common waveform center value operates as a voltage follower. In this case, leave it open.
10
Data Sheet S15817EJ2V0DS
PD161623
(2/2)
Symbol FBRSEL Pin Name Pad No. VCOM setting external 117 circuit select I/O Input Function This pin is used to select the method of adjusting the amplifier for setting the common waveform center value used to set the COMMON drive waveform center level. FBRSEL = H: Voltage follower circuit used (VCOMR connected to VCOM internally) FBRSEL = L: External feedback resistor used CVPH, CVPL, Basis power supply pin for -corrected power supplies D/A converter value setting 102, 101, 100, 99 139 to 132 Input These pins set the reference voltage of the amplifier for setting the VCOM value used to set the COMMON drive waveform center level. These pins are valid when the VCOM output center value setting register (R29) = 00H and BGRS (R25: D6) = 0. For more details, refer to 5.5 Common Adjustment Circuit. Output This is operational amplifier output pin for the g-corrected power supplies. Normally, this pin connects capacitor of 1.0 F.
5
CVNH, CVNL DAC0 to DAC7
Remark T.B.D. (To be determined.) 3.6 Test or Other Pins
Symbol
TOUT0 to TOUT17,
Pin Name Source output
Pad No. 34 to 17, 41
I/O
Function
Output This is output pin when PD161623 is in test mode. Normally, leave it open. Output These pins are to set up test mode of PD161623. Normally, fixed it to VSS.
TOSCO TSTRTST, TSTVIHL, TOSCI, TOSCSELI, TOSCSELO, TBSEL1, TBSEL2, PSX1 SI, SCL TBGR Test input/output Test input COM adjustment
37, 36, 40, 39, 38, 129, 130, 78 75, 76 131
Input
These pins are to set up test mode of PD161623. Normally, fixed it to either VDD1 or VSS. This is output pin when PD161623 is in test mode. Normally, leave it open.
I/O
DUMMY
Dummy
1 to 16, 111, 112, 153 to 192, 458 to 467, 731 to 737
-
Dummy pin
Data Sheet S15817EJ2V0DS
11
PD161623
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The I/O circuit types of each pin and recommended connection of unused pins are described below. 5
Pin Name PSX0 /RESET Input Type Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger - CMOS CMOS - Schmitt trigger - - - - - - - - - - - - - - - - - - - - - - - - - - - - Schmitt trigger CMOS I/O Input Input Input Input I/O Input Output Input Input Output Input Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Output Output Input Input Input Input Input Input Input Input Input Input Input Input Input Power Supply VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VS VS VDD2 VS VS VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD1 VDD1 VDD1 VDD1 VDD2 Recommended Connection of Unused Pins Mode setting pin Always reset on power application Connect to VDD1 (when i80 series interface) Mode setting pin - Register setting pin Leave open Input external clock (in OSCSEL = H mode) Leave open (in OSCSEL = H mode) Leave open Mode setting pin Always connect to the gate driver Always connect to the gate driver Always connect to the gate driver Always connect to the gate driver Leave open Always connect to the power IC Always connect to the power IC Always connect to the power IC Always connect to the power IC Always connect to the power IC Leave open (FRBSEL = H) Leave open Leave open Leave open (BGRS = 0 [R25]) Leave open (FRBSEL = H) Leave open Leave open Connect to VSS Connect to VSS Connect to VSS Connect to VSS Connect to VSS Connect to VSS Connect to VSS Connect to VSS Connect to VSS Connect to VDD1 or VSS Connect to VDD1 or VSS Connect to VDD1 or VSS Connect to VDD2 or VSS Note 1 - - 1 - 2 - - - - 3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 3
5 5 5
/RD(E) C86 D0 to D17 RS OP0 to OP7 OSCIN OSCOUT CSTB OSCSEL GOE1 GOE2 GSTB GCLK LPMP DCON RGONP VCD11, VCD12 VCD2 VCE VCOM VCOUT1 VCOUT2
5 5
BGRIN VCOMR
TOUT0 to TOUT17
TOSCO TSTRTST TSTVIHL TOSCI TOSCSELI TOSCSELO TBSEL1 TBSEL2 TBGR PSX1 SCL SI DTX FBRSEL
Notes 1. Connect to VDD1 or VSS, depending on the mode selected. 2. Input either H or L by CPU, depending on the register selected. 3. Connect to VDD2 or VSS, depending on the mode selected. 12
Data Sheet S15817EJ2V0DS
PD161623
5. DESCRIPTION OF FUNCTIONS
5.1 CPU Interface 5.1.1 Selection of interface type The PD161623 chip transfers data using a 18-bit bi-directional data bus (D17 to D0), 16-bit bi-directional data bus (D15 to D0). Setting the polarity of the PSX0 pin as either H or L enables the selections shown in Table 5-1 below. Table 5-1.
PSX0 H L Mode 18-bit parallel 16-bit parallel /CS /CS /CS RS RS RS /RD (E) /RD (E) /RD (E) /WR (R, /W) /WR (R, /W) /WR (R, /W) C86 C86 C86 D17, D16 D17, D16 Hi-Z
Note
D15 to D8 D15 to D8 D15 to D8
D7 to D0 D7 to D0 D7 to D0
Note Hi-Z: High impedance 5.1.2 Selection of data transfer mode In the PD161623, when the 16-bit parallel interface is selected, there are two types of modes to transfer data to display RAM. The mode can be selected as follows with the DTX command. When using the 16-bit parallel interface and the 1-pixel/18-bit mode (DTX = H) is selected, one pixel of display data must be transferred every two words, as shown in Figure 5-4. At this time, the data of DB15 to DB9 is treated as invalid data. When the 1-pixle/16-bit mode (DTX = L) is selected, one pixel of display data is transferred every word. However, because one pixel data is 16 bits long, the display color range is restricted to 65,536. When the 18-bit parallel interface is used, the data transfer method is fixed to 1-pixel/18-bit mode, regardless of the setting of the DTX pin. Because the display RAM in the PD161623 has a 1-pixel/18-bit configuration, when using the 1-pixel/16-bit mode (DTX = L), it will be necessary to add supplementary data for the two-bit data deficiency that occurs when (16-bit) data is transferred from the CPU. For the relationship between the display data and the supplementary data set by the data supplement register, refer to Figure 5-3. Table 5-2.
PSX0 H L Interface Mode 18-bit parallel 16-bit parallel DTX X
Note
Mode 1-pixel/18-bit 1-pixel/18-bit 1-pixel/16-bit
H L
Note X: Don't care (H or L)
Data Sheet S15817EJ2V0DS
13
PD161623
Table 5-3. Data Supplement Register
Supplemented Display Data CD12 CD0 When 1-pixel/16-bit mode is used, the value set by this flag is stored in the display RAM as D12 data. When 1-pixel/16-bit mode is used, the value set by this flag is stored in the display RAM as D0 data.
Figure 5-1. Relationship between Data Bus and Display RAM Data (18-bit parallel interface) -
Data bus side DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 18-bit data DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D17
D16
D15
D14 Dot 1
D13
D12
D11
D10
D9 D8 Dot 2 1st pixel
D7
D6
D5
D4
D3 D2 Dot 3
D1
D0
Display RAM side
Figure 5-2. Relationship between Data Bus and Display RAM Data - (1-pixel/18-bit mode [DTX = H], 16-bit parallel interface)
Data bus side DB8 DB7 DB6 9-bit data (1st word) DB5 DB4 DB3 DB2 DB1 DB0 DB8 DB7 DB6 DB5 9-bit data (2nd word) DB4 DB3 DB2 DB1 DB0
D17
D16
D15
D14 Dot 1
D13
D12
D11
D10
D9 D8 Dot 2 1st pixel
D7
D6
D5
D4
D3 D2 Dot 3
D1
D0
Display RAM side
Note When in used 16-bit parallel interface, DB15 to DB9 is treated as invalid data. Figure 5-3. Relationship between Data Bus and Display RAM Data - (1-pixel/16-bit mode [DTX = L], 16-bit parallel interface)
Data bus side DB15 DB14 DB13 DB12 DB11 DB10 DB9 16-bit data DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Data supplement function CD12
Note
CD0
Note
D17
D16
D15 D14 Dot 1
D13
D12
D11
D10
D9 D8 Dot 2 1st pixel
D7
D6
D5
D4
D3 D2 Dot 3
D1
D0
Display RAM side
Note When In used 16-bit parallel interface, display RAM data D12 and D0 are added to the 16-bit data by the data supplement register (R4), and written to the display RAM as 18-bit data.
14
Data Sheet S15817EJ2V0DS
PD161623
Figure 5-4. 16-bit Parallel Interface Date Transfer (1-pixel/18-bit mode [DTX = H]) -
/CS
RS
/WR
D15
Invalid
Invalid
Invalid
Invalid
D14
Invalid
Invalid
Invalid
Invalid
D13
Invalid
Invalid
Invalid
Invalid
D9
Invalid
Invalid
Invalid
Invalid
D8
D17
D8
D17
D8
D7
D16
D7
D16
D7
D6
D15
D6
D15
D6
D1
D10
D1
D10
D1
D0
D9
1st word 1-pixel data
D0
2nd word
D9
1st word 1-pixel data
D0
2nd word
Data Sheet S15817EJ2V0DS
15
PD161623
5.1.3 Parallel interface When the parallel interface has been selected, setting the C86 pin as either H or L enables a direct connection to an i80 series or M68 series CPU (see Table 5-4 below). Table 5-4.
C86 H L Mode M68 series CPU i80 series CPU /RD /WR /RD (E) E /WR (R, /W) R, /W PSX0 H L H L D17, D16 D17, D16 Hi-Z Hi-Z
Note
D15 to D8 D15 to D8 D15 to D8 D15 to D8 D15 to D8
D7 to D0 D7 to D0 D7 to D0 D7 to D0 D7 to D0
D17, D16
Note
Note Hi-Z: High impedance. Leave it open. The data bus signal is identified according to the combination of the RS, /RD (E), and /WR (R, /W) signals, as shown in the following Table 5-5. 5
Common RS H H L L M68 series CPU R, /W H L H L
Table 5-5.
i80 series CPU /RD L H L H /WR H L H L Function Read display data Write display data Prohibited Write to control index register
16
Data Sheet S15817EJ2V0DS
PD161623
(1) i80 Series Parallel Interface When i80 series parallel data transfer has been selected, data is written to the PD161623 at L period of the /WR signal. The data is output to the data bus when the /RD signal is L. Figure 5-5. i80 Series Interface Data Bus Status
/CS
/WR
/RD
Hi-Z DBn Data write Valid data Data read
Hi-Z
(2) M68 Series Parallel Interface When M68 series parallel data transfer has been selected, data is written at the H period of the E signal when the R,/W signal is L. In a data read operation, data is output at the rising edge of the E signal in a period when the R,/W signal is H. The data bus is released (Hi-Z) at the falling edge of the E signal. Figure 5-6. M68 Series Interface Data Bus Status (When data read)
/CS
R,/W
E
Hi-Z
Hi-Z DBn
Valid data
Hi-Z
Data Sheet S15817EJ2V0DS
17
PD161623
5.1.4 Chip select The PD161623 has two chip select pins (/CS). The CPU parallel interface can be used only when /CS = L. When the chip select pin is inactive, D0 to D17 are set to high impedance (invalid) and input of RS, /RD, or /WR is not active. 5.1.5 Access to display data RAM and internal registers When the CPU accessed the PD161623, the CPU only has to satisfy the requirement of the cycle time (tCYC) and can transfer data at high speeds. Usually, it is not necessary for the CPU to take wait time into consideration. A high-speed RAM write function, as well as the ordinary RAM write function, is provided for writing data to the display data RAM. By using the high-speed write function, data can be written to the display RAM at an access speed two times faster than that of the ordinary RAM write function. Therefore, applications, such as motion picture display where the display data must be rewritten at high speeds, can be supported. For details, refer to 5.2.5 High-speed RAM write mode Dummy data is not required when writing data. In the PD161623, only for reading display data, needs dummy data. This relationship is shown in Figure 5-7. Note that when in write mode of data at high speed for data read mode of read cycle time, this mode equals to normal mode.
18
Data Sheet S15817EJ2V0DS
PD161623
Figure 5-7. Image of internal access to display RAM Writing
/WR
DATA
n
n+1
n+2
n+3
Bus Holder
n
n+1
n+2
n+3
Write Signal
Reading
/WR
/RD
DATA
n
n
n
n+1
Address Preset
Read Signal
Column Address
Preset n
Increment n+1
n+2
Bus Holder
n
n
n+1
n+2
Address set #n
Dummy read
Data read #n
Data read #n
Data Sheet S15817EJ2V0DS
19
PD161623
5.2 Display Data RAM This RAM stores dot data for display and consists of 3,168 bits (176 x 18) x 240 bits. Any address of this RAM can be accessed by specifying an X address and an Y address. Display data D0 to D17 transmitted from the CPU corresponds to the pixels on the LCD (refer to Table 5-8). Figure 5-8. Display Data RAM -
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Dot 1 Dot 2 Pixel 1 (= 1 X address) Dot 3
LCD panel
Pixel 1 Pixel 1
Pixel 2 Pixel 2
Pixel 3 Pixel 3
Pixel 4 Pixel 4
Pixel 5 Pixel 5
Pixel 6 Pixel 6
Pixel 7 Pixel 7
Pixel 8 Pixel 8
00H
01H
02H
03H
04H
05H
06H
07H
5.2.1 X address circuit An X address of the display data RAM is specified by using the X address register (R6) as shown in Figure 5-9. The specified X address is incremented by one each time display data is written or read. In the increment mode, the X address is incremented up to AFH. If more display data is written or read, the Y address is incremented, and the X address returns to 00H. 5.2.2 Y address circuit A Y address of the display data RAM is specified by using the Y address register (R7) as shown in Figure 5-9. The Y address is incremented each by one when one each time display is written or read and X address is incremented to last address. When the Y address has been incremented up to EFH and the X address up to the final address, if further display data is read or written, the X and Y addresses return to 00H.
20
Data Sheet S15817EJ2V0DS
PD161623
5.2.3 Column address circuit When the contents of the display data RAM are displayed, column addresses are output to the source output pins as shown in Figure 5-9. The correspondence relationship between the column addresses of the display RAM and source outputs can be reversed by the ADC flag (source driver direction select flag) of control register 1 (R0) as shown in Table 5-6. This reduces the restrictions on chip layout when the LCD module is assembled. Table 5-6. Relationship between Column Address of Display RAM and Source Output -
Source Output ADC 0 1 Y1 000H 20FH Y2 001H 20EH Column address Column address Y527 20EH 001H Y528 20FH 000H
Figure 5-9. PD161623 RAM Addressing
Source output ADC=0 ADC=1 X-address Column addre 000H D17--D12 Gate output R,/L=H R,/L=L O1 O2 | O87 O88 O89 O90 | O239 O240 O240 O239 | O90 O89 O88 O87 | O2 O1 Y-address ADR=0 ADR=1 00H 01H | 56H 57H 58H 59H | EEH EFH EFH EEH | 59H 58H 57H 56H | 01H 00H Scan direction Y1 Y528 Y2 Y527 000H 001H D11--D6 1st pixel Y3 Y526 002H D5---D0 Y4 Y525 003H D17--D12 Y5 Y524 001H 004H D11--D6 2nd pixel Y6 Y523 005H D5---D0 --- ----- ----- ----- --20AH D17--D12 Y523 Y6 Y524 Y5 AEH 20BH D11--D6 1st pixel Y525 Y4 20CH D5---D0 Y526 Y3 20DH D17--D12 Y527 Y2 AFH 20EH D11--D6 2nd pixel
Display area
Data Sheet S15817EJ2V0DS
21
PD161623
5.2.4 Arbitrary address area access (window access mode (WAS)) With the PD161623, any area of the display RAM selected by the MIN.*X/Y address registers (R8 and R10) and MAX. X/Y address registers (R9 and R11) can be accessed. 5 When WAS of data access control register (R5) is set to 1, the window access mode is then selected and accessed by setting only address area of the MIN.X/Y address registers and MAX.*X/Y address registers. . The address scanning setting is also valid in this mode, in the same manner as when data is normally written to the display RAM. In addition, data can be written from any address by specifying the X address register (R6) and Y address register (R7). Note that the display RAM must be accessed after setting the X address register (R6) and Y address register (R7) if the window access area has been set or changed by the MIN. X/Y address register or MAX. X/Y address register. Figure 5-10. Example of Incrementing Address when in Window Access Mode -
MIN. . X address Start point 00H MAX. . X address AFH
00H
MIN. . Y address
. . .
MAX. . Y address EFH End point
Cautions 1. When using the window access mode, the relationship between the start point and end point shown in the table below must be established.
Item X address Y address Address Relationship 00H MIN.X address X address (R6) MAX.X address AFH 00H MIN.Y address Y address (R7) MAX.Y address EFH
2. If invalid address data is set as the MIN./MAX. address, operation is not guaranteed. 5 3. Do not specify any value other than the address value 2n-2 (n = 1 to 88) for the X address in the - high-speed RAM access mode. The operation is not guaranteed if invalid address data is set. 4. Access the display RAM after setting the X address register (R6) and Y address register (R7) if the window access area has been set or changed by the MIN. X/Y address register or MAX. X/Y address register.
22
Data Sheet S15817EJ2V0DS
PD161623
Figure 5-11. Example of Sequence in Window Access Mode -
Start
Data access control register (R5) (WAS = 1)
Sets window access mode.
MIN. . X address register (R8) Sets start point. MIN. . Y address register (R10)
MAX. . X address register (R9) Sets end point. MAX. . Y address register (R11)
X address register (R6) Y address register (R7) Write display data
Data No
Writing complete? Yes End
Data Sheet S15817EJ2V0DS
23
PD161623
5.2.5 High-speed RAM write mode With the PD161623, two types of access modes can be selected for accessing the display RAM. The PD161623 has a high-speed RAM write function, as well as an ordinary RAM write function. By using the highspeed write function, data can be written to the display RAM at an access speed two times faster than that of the ordinary RAM write function. Therefore, applications, such as motion picture display where the display data must be rewritten at high speeds, can be supported. When the high-speed RAM write mode is selected by using BSTR of the data access control register (R5), data is temporarily stored in an internal register of the PD161623. When data of 36 bits (18 bits x 2) has been stored in the register, it is written to the display RAM. It is also possible to write the next data to the internal register while the first data is being written to the RAM. In the high-speed RAM write mode, however, the CPU must transmit data in units of 2 pixel data (1-pixel/18-bit mode: 36-bit, 1-pixel/16-bit mode: 32-bit) have been written to the internal register. If data of less than 2-pixel data is transmitted in the high-speed RAM write mode, this data is not written to the display RAM. Therefore, CPU data is not reflected on the LCD display even if it is transmitted. In this case, the data that is not reflected remains stored in the register. When the next data is transmitted, it is written to the register from where the preceding data is stored. However, if the chip select signal is disserted inactive (/CS = H) in the middle of data transfer, and then asserted active again and when the display data write is set, the register is initialized. Consequently, the data stored in the register is lost. It is therefore recommended to transmit display data in 2-pixel units when using the high-speed RAM write mode. Figure 5-12. Image of Operation in High-speed Write Mode
Display RAM
36-bit
36-bit
36-bit
36 36
36-bit register
36
36
18 18
Data supplement function
18
Data supplement register (R4)
Display data
18/16 Parallel/Serial interface circuit
Caution Do not specify any value other than the address value 2n - 2 (n = 1 to 88) for the X address (R6) in the high-speed RAM access mode. The operation is not guaranteed if invalid address data is set.
Data Sheet S15817EJ2V0DS
24
PD161623
Figure 5-13. Example of Sequence in High-Speed RAM Write Mode (with 18-Bit Parallel Interface) -
Start
High speed RAM write mode setting (R5: BSTR[D6] = 1)
Sets the high-speed RAM write mode.
X address setting register (R6)Note
Y address setting register (R7)
Write display data
1-pixel (2n - 1) of display data (18 bit) 2-pixel (2n) of display data (18 bit) Data write sequence (writing data in 2-pixel units)
End of data Yes Next processing
No
End
n: n 1 Note Do not specify any value other than the address value 2n - 2 (n = 1 to 88) for the X address (R6) in the high-speed RAM access mode. The operation is not guaranteed if invalid address data is set.
Data Sheet S15817EJ2V0DS
25
PD161623
5.3 Oscillator The PD161623 has a CR oscillator (with external R resistance), which generate the display clock. When OSCSEL is L, an internal CR oscillator is selected. On the other hand, leave both OSCIN and OCSOUT pin open. When OSCSEL is H, an external connection oscillator is selected. Connect 42 k resistance between OSCIN an OSCOUT pin (when in used 240 lines). This oscillator also has a calibration function, which is available by itself to set the number of frame frequency of display driving. Frame frequency calibration is set by calibration register (R45). The time to select one line is set by the calibration start and stop commands. Figure 5-14. Frame Frequency Calibration
Calibration command
Start/Stop Register
OSC
n-bit counter
Internal clock
The calibration function involves counting the number of oscillation clocks generated between the start and stop signals and storing that number in a register. The number of oscillation clocks is then continually compared with this register value in subsequent operations, and the time of the clock number stored in the register is set as 1 line selection time, and used as the internal reference clock. Using the time to set calibration (tcal) can be selected either tcal or tcal x 2 through control register 2 (R1): LTS. Figure 5-15. Calibration Function Timing (LTS [R1] = 0)
Calibration start tcal (1 line time)
Calibration stop
tcal = 1/(fFRAME x n) fFRAME = Frame frequency n: Line numbers
1
OSC1
2
3
4
5
6
7
1
OSC2
2
3
4
26
Data Sheet S15817EJ2V0DS
PD161623
5.4 Display Timing Generator 5.4.1 Display timing The PD161623 generates the TFT-:CD drive timing inside the PD161623. The TFT-LCD panel is driven at the timing of one line selection period generated based on the calibration time (tcal) set by the calibration function, as shown in the figure below. One line selection period is made up of a pre-charge period, a source output period, and the PD161623 output control clock. The pre-charge and source output periods are set by the pre-charge period setting register (R46) and calibration register (R45), respectively, based on the following expressions. 1 line selection period = tcal Pre-charge period = tpr Source output period = tsout tcal: Calibration setting time [R45] tpr = (1/fOSC) x (CLKpr + 2 CLK) tsout = tcal - (tpr + 3 CLK) CLKcal: Calibration setting time (tcal) clock number = tcal / (1/fOSC) CLKpr: Pre-charge peiod setting register clock number [R46: PLIMn] n 1 CLK = 1/fOSC fOSC: Oscillator frequency
Data Sheet S15817EJ2V0DS
27
PD161623
Figure 5-16. 1-line Select Time
1 line select time
1 CLK
fOSC
Output control basis clock
1 0
1 1 1 2 3 4 5 6 7 8 9
1 0
1 1 1 2 3 4 5 6
Output switching time (1 CLK)
Pre-charge time
2 CLK
Source output time: tsout
2 CLK
tpr
tcal1
4 CLK
Sn
GCLK GSTB GOE1
Gn
VCOUT
28
Data Sheet S15817EJ2V0DS
PD161623
The display timing generator generates the timing signals for the internal timing of the source driver and for the gate driver. The output timings for normal operation, for normal operation stand-by mode, and for stand-by mode normal operation, are shown below. Figure 5-17. During Normal Operation (during line inversion)
GSTB
Data output line no. GCLK GOE1
240
dummy
1
2
3
4
5
240
dummy
1
2
GOE2
Sn
VCOUT
G240
G1
G2
G3
Data Sheet S15817EJ2V0DS
29
PD161623
Figure 5-18. Normal Operation Stand-by Input (during line inversion)
(1) (2)
GSTB
Data output line no. GCLK GOE1
240
dummy
1
2
3
4
5
240
dummy
GOE2
Sn
VCOUT
G240
G1
G2
G3
G4
Stand-by command input
Stand-by mode start
Stand-by statement
30
Data Sheet S15817EJ2V0DS
PD161623
Figure 5-19. Normal Operation Stand-by Input (during line inversion) (1) Reference
1 line select time (3 line)
1 CLK
1 line select time (4 line)
fOSC
GSTB
GCLK
GOE1
GOE2
Sn VSS
G2
G3
G4
VCOUT VSS Stand-by command Stand-by mode start
Data Sheet S15817EJ2V0DS
31
PD161623
Figure 5-20. Normal Operation Stand-by Input (during line inversion) (2) Reference
Stand-by time 1 line select time (dummy line)
1 CLK
fOSC
Oscillation stop
GSTB
GCLK
GOE1
GOE2 Sn VSS
G240
G3
G4 All gate on VCOUT VSS Stand-by command
32
Data Sheet S15817EJ2V0DS
PD161623
Figure 5-21. Stand-by Return to Normal Operation (during line inversion)
GSTB
Data output line no. GCLK GOE1
dummy
1
2
3
4
5
GOE2
Sn
VCOUT
G240
G1
G2
G3
G4
Stand-by release command input
Data Sheet S15817EJ2V0DS
33
PD161623
5.5 Common Adjustment Circuit To generate common output, the center voltage of the common waveform is output from the VCOM pin along with output of a 0 to VS (V) square waveform from the VCOUT1 pin and 0 to VDD1 (V) from VCOUT2. The level of the VCOM output can be adjusted using as external resistor. 5 Figure 5-22. Common Adjustment Circuit
R29
VS R25 (PVCOM)
D/A converter
R25 (BGRS)
VBGR
Rectangle waveform value VCOUT1: Vp-p = VS VCOUT2: Vp-p = VCC1
BGRIN DAC7 DAC0
VCOMR FBRSEL
VCOM
VCOUT1, VCOUT2
R1 R3 R2
C1 VCOMMON VS, VCC1 0V
VCOMMON waveform center setting
The VCOM voltage formulas are shown below. 5 COM voltage = (1+R1/R2) x VBGR x ( / 256) VBGR = 3.0 V TYP. : Setting of VCOM electric volume register (R29) 5 < When internal power supply is used 2 (D6 of R25: BGRS = 0, D3 of PVCOM = 1) > COM voltage = (1+R1/R2) x VS x ( / 256) : Setting of VCOM electric volume register (R29) 5 COM voltage = (1+R1/R2) x VBGRIN VBGRIN = External supply voltage (voltage input from BGRIN) 5 Use the values listed below as a guideline. The user is responsible for ultimately determining the resistance values and recommended values based on careful evaluation on actual panels. R1: 200 k R2: 51 to 100 k R3: 51 to 100 k C1: 10 F 34
Data Sheet S15817EJ2V0DS
PD161623
5.6 Rectangular Signal Generator This circuit generates a common rectangular signal. A rectangular wave of 0 to VS (V) is output from the VCOUT1 pin, and a wave of 0 to VDD2 (V) is output from the VCOUT2 pin. The common output wave necessary for driving an LCD can be generated by connecting an external circuit as shown in Figure 5-22. 5.7 Reference Voltage Generator (VBGR) The PD161623 has a reference voltage generator for the voltage regulator. This reference voltage generator generates a constant voltage from VDD2. The constant voltage generated by this circuit is connected to the input of the operational amplifier that adjusts the center level of the COMMON drive output, via a D/A converter. By using this voltage, therefore, the center level of the COMMON drive output can be kept constant, without being affected by fluctuations in the supply voltage. The common waveform output necessary for driving an LCD can be generated by connecting the external circuit show in Figure 5-16. When the internal reference voltage generator is not used (R25: BGRS = 1), directly input the reference voltage to the operational amplifier that adjusts the center level of the COMMON drive output. 5.8 D/A Converter Circuit The PD161623 is provided with an internal D/A converter to adjust the voltage of the reference voltage generator for the voltage regulator. This D/A converter divides the constant voltage generated by the reference voltage generator (VBFR) by 256, and a level of voltage between VBGR and VSS can be selected by setting the VCOM electronic volume register (R29). In addition, this D/A converter also has a function to select a level by using an external pin. If the set value of the VCOM electronic volume register (R29) is 00H, the set statuses of the DAC7 to DAC0 pins are valid. Table 5-7. Setting of VCOM Electronic Volume Register (R25: BGRS = 0)
EV7 DAC7 EV6 DAC6 EV5 DAC5 EV4 DAC4 EV3 DAC3 EV2 DAC2 EV1 DAC1 EV0 DAC0 DACn set 00H 01H 02H 03H FEH FFH 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 value 0 2 3 4 255 256 DACn Remark R29
Data Sheet S15817EJ2V0DS
35
PD161623
5.9 -Curve Correction Power Supply Circuit The PD161623 includes a -curve correction power supply circuit. If the internal -curve correction matches the LCD characteristics, no external components are necessary. This power circuit has white level and black level reference voltage generators on the positive and negative polarity sides, and also supports unbalanced driving. The reference voltage generators consist of a D/A converter and an operational amplifier and divide VS to VSS by 256. One level of voltage can be selected by using the -contrast value setting register1 to 4 (R36 to R39) Figure 5-23. -Curve Correction Circuit
VS SPH2 custom SNL2 VSS VRH
D/A (R37)
VPH
SPH1 V0
D/A (R36)
VNH
SNL1
SNH1
V5 D/A (R39) VPL SPL1 VRL1
D/A (R38)
VNL
SNH2 VS SPL2 VRL2 VSS
36
Data Sheet S15817EJ2V0DS
PD161623
Figure 5-24. Relationship of TFT Drive Voltage (Normally White)
VS VPH VNH Black
VPL VNL VSS Positive polarity Negative polarity
White
Drive Level VPH VNH VPL VNL Positive polarity, black Negative polarity, white Positive polarity, black Negative polarity, white
Setting Register Contrast value setting register 1 Contrast value setting register 2 Contrast value setting register 3 Contrast value setting register 4 R36 R37 R38 R39
The value of each amplifier output can be expressed as follows and the value of can be set as shown in Table 5-8 and 5-9 by using the contrast value registers (R36, R37, R38, and R39) VNL, VPL, VNH, VPH = ( / 256) x VS Caution The usable range in which each output level of VPH, VNH, VPL, and VNL can be set depends on the
-curve.
Table 5-8. -Contrast Value Setting and Electronic Volume Register Setting 1 (VPH, VNL)
R36 R37 00H 01H 02H 03H FEH FFH GPH7 GNH7 0 0 0 0 1 1 GPH6 GNH6 0 0 0 0 1 1 GPH5 GNH5 0 0 0 0 1 1 GPH4 GNH4 0 0 0 0 1 1 GPH3 GNH3 0 0 0 0 1 1 GPH2 GNH2 0 0 0 0 1 1 GPH1 GNH1 0 0 1 1 1 1 GPH0 GNH0 0 1 0 1 0 1 value Setting or Status Setting Fixed to VS (Amplifier OFF) 255 254 253 2 1
Data Sheet S15817EJ2V0DS
37
PD161623
Table 5-9. -Contrast Value Setting and Electronic Volume Register Setting 2 (VPL, VNL)
R36 R37 00H 01H 02H 03H FEH FFH GPL7 GNL7 0 0 0 0 1 1 GPL6 GNL6 0 0 0 0 1 1 GPL5 GNL5 0 0 0 0 1 1 GPL4 GNL4 0 0 0 0 1 1 GPL3 GNL3 0 0 0 0 1 1 GPL2 GNL2 0 0 0 0 1 1 GPL1 GNL1 0 0 1 1 1 1 GPL0 GNL0 0 1 0 1 0 1 value Setting or Statement Setting Fixed to VS (Amplifier OFF) 1 2 3 254 255
The relationship between the setting of the contrast value setting register and the driven waveform is explained next, taking the -curve in Figure 5-23 as an example. Table 5-10. Switch Status when -Curve Correction Power Supply Circuit is not used (R36, R37, R38, R39 = 00H)
Polarity Positive Negative Switch Status SPH1 X X SNL1 X X SNH1 X X SPL1 X X SPH2 ON OFF SNL2 OFF ON SNH2 OFF ON SPL2 ON OFF
Remark X: Switch is normally OFF with the amplifier OFF. Relationship of drive voltage (normally white)
VS VPH VNH Black
VPL VNL VSS Positive polarity Negative polarity
White
38
Data Sheet S15817EJ2V0DS
PD161623
Table 5-11. Switch Status when -Curve Correction Power Circuit is used (R36, R37, R38, R39 = other than 00H)
Polarity Positive Negative Switch Status SPH1 ON OFF SNL1 OFF ON SNH1 OFF ON SPL1 ON OFF SPH2 x x SNL2 x x SNH2 x x SPL2 x x
Remark x: Switch is normally OFF Relationship of drive voltage (normally white)
VS VPH VNH Black
VPL VNL VSS Positive polarity Negative polarity
White
Data Sheet S15817EJ2V0DS
39
PD161623
Figure 5-25. TFT Drive Voltage Level
VS SPH2
SNL2 VSS VRH
D/A (R37)
VPH
SPH1 V0
D/A (R36)
VNH
SNL1
SNH1
Drive voltage range
V5 VRL1 VRL2
D/A (R39)
VPL
SPL1
D/A (R38)
VNL
SNH2 VS SPL2
VSS
40
Data Sheet S15817EJ2V0DS
PD161623
Table 5-12. -Curve Correction Circuit ( -Correction Resistance)
Glay Scale 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Dn+5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Display Data Dn+4 Dn+3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Dn+2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Dn+1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Total Dn 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Resistance (k) r1 1.587 r2 1.226 r3 2.453 r4 3.390 r5 4.112 r6 4.905 r7 1.731 r8 1.443 r9 1.587 r 10 1.515 r 11 1.082 r 12 1.082 r 13 1.154 r 14 1.226 r 15 1.298 r 16 1.082 r 17 0.649 r 18 0.721 r 19 0.794 r 20 0.721 r 21 0.794 r 22 0.505 r 23 0.577 r 24 0.577 r 25 0.577 r 26 0.505 r 27 0.433 r 28 0.433 r 29 0.433 r 30 0.433 r 31 0.505 r 32 0.361 r 33 0.433 r 34 0.433 r 35 0.433 r 36 0.433 r 37 0.433 r 38 0.433 r 39 0.505 r 40 0.433 r 41 0.433 r 42 0.433 r 43 0.505 r 44 0.361 r 45 0.433 r 46 0.433 r 47 0.361 r 48 0.361 r 49 0.361 r 50 0.361 r 51 0.433 r 52 0.433 r 53 0.433 r 54 0.505 r 55 0.505 r 56 0.505 r 57 0.721 r 58 0.721 r 59 0.866 r 60 0.866 r 61 1.587 r 62 2.597 r 63 2.597 r 64 12.047 r 65 7.719 80.000 Output Voltage (V) Positive Voltage Negative Voltage 4.901 0.107 4.824 0.190 4.671 0.356 4.459 0.586 4.202 0.864 3.895 1.196 3.787 1.313 3.697 1.411 3.598 1.519 3.503 1.621 3.436 1.694 3.368 1.768 3.296 1.846 3.219 1.929 3.138 2.017 3.070 2.090 3.030 2.134 2.985 2.183 2.935 2.236 2.890 2.285 2.840 2.339 2.809 2.373 2.773 2.412 2.737 2.451 2.701 2.490 2.669 2.524 2.642 2.554 2.615 2.583 2.588 2.612 2.561 2.642 2.529 2.676 2.507 2.700 2.480 2.729 2.453 2.759 2.426 2.788 2.399 2.817 2.372 2.847 2.344 2.876 2.313 2.910 2.286 2.939 2.259 2.969 2.232 2.998 2.200 3.032 2.178 3.057 2.151 3.086 2.124 3.115 2.101 3.140 2.078 3.164 2.056 3.188 2.033 3.213 2.006 3.242 1.979 3.271 1.952 3.301 1.921 3.335 1.889 3.369 1.858 3.403 1.812 3.452 1.767 3.501 1.713 3.560 1.659 3.618 1.560 3.726 1.398 3.901 1.235 4.077 0.482 4.893
Data Sheet S15817EJ2V0DS
41
PD161623
5.10 Partial Display Mode The PD161623 is provided with a function that allows sections within the screen to be displayed separately (partial display mode). The start line of the area to be displayed in partial display mode is set using the partial display area start line register (R20, R21), the number of lines in the area to be displayed is set using the partial display area line count register (R22, R23), and the color of the area not to be displayed is set using the partial off area color register (R19). If "1" is set in the partial display area line count registers (R22, R23), the partial display areas each become 1 line. If "0" is set, there are no partial display areas but only normal display areas. The non-display area indicated by R20 and R22 is called Partial 1, and the non-display area indicates by R21 and R23 is called Partial 2. The Partial 2 setting is enabled only when the Partial 1 setting has been performed (when R22 0). Therefore, to set only one area as a non-display area, perform only the setting for Partial 1. Low power consumption cannot be achieved if only the partial mode is set. If low power consumption is required, the mode must be switched to the 8-color mode. Figure 5-26. Partial Display Mode
00H
01H
02H
03H
...
ADH
AEH
AFH
Display start line (00H)
Partial display start line (R20, R21)
Partial display area line number(R22, R23)
Section not displayed
Cautions 1. The "scroll step count register (R17)" command is ignored in the partial display mode. 2. The specified partial areas must not directly overlap, and the Partial 1 area and Partial 2 area must be separated by at least one line. If the areas overlap, only the Partial 1 settings are valid, and partial display is not performed for the Partial 2 area. 3. When setting the partial display areas, be sure to observe the following relationship. "00H" R20 (R21) R22 (R23) "AFH" The following sequence is recommended to avoid display malfunction when switching from normal display mode to partial display mode and vice versa.
42
Data Sheet S15817EJ2V0DS
PD161623
(1) Recommended sequence for switching from normal display mode to partial display mode
DISP1 = 1
R0
D7 D2
<1> Display off
PGDn setting Display data overwrite (for partial display)
R19 D0
<2> Partial off area color register setting
Note1
<3> Display data overwrite
Note1
D7
P1SLn, P2SLn setting
R20, R21
<4> Partial display area start line setting D0 D7
Note1
P1AWn, P2AWn setting DTY = 1, COLOR = 1 DISP1 = 0
R22, R23 R0 R0
<5> Partial display area line count setting D0 D4, D2 D7 <6> Partial display mode, 8-color mode <7> Display on
Note1
Note2
Notes 1. <2> to <5> can be executed in any order. 2. <6> must be executed after <4> and <5> have been set.
Data Sheet S15817EJ2V0DS
43
PD161623
(2) Recommended sequence for switching from partial display mode to normal display mode
DISP1 = 1 Display data overwrite (for normal display) DTY = 0, COLOR = 0 DISP1 = 0
Note
R0
D7
<1> Display off <2> Display data overwrite
Note
R0 R0
D4, D2 D7
<3> Partial display mode, 260,000-color mode <4> Display on
Note <2> to <3> can be executed in any order. (3) Recommended sequence for switching from partial display mode to partial display mode (switching the partial display area)
DISP1 = 1 (Display data overwrite)
R0
D7
<1> Display off <2> Display data overwrite Notes
Note1, 2
D7
P1SLn, P2SLn setting
R20, R21
<3> Partial display area start line setting D0 D7
Note1
P1AWn, P2AWn setting DTY = 1 DISP1 = 0
R22, R23 R0 R0
<4> Partial display area line count setting D0 D4 D7 <5> Partial display mode <6> Display on
Note3
Note1
Notes 1. <2> to <4> can be executed in any order. 2. Execute <2> only when necessary. 3. <5> must be executed after <3> and <4> have been set.
44
Data Sheet S15817EJ2V0DS
PD161623
(4) Partial display setting examples Setting A-1
Register Partial display area start line register (R20, R21) Partial display area line count register (R22, R23) Setting Value 00H 78H Details of Setting Value Sets Y address 00H Sets an area of 120 lines
Setting A-2
Register Partial display area start line register (R20, R21) Partial display area line count register (R22, R23) Setting Value 78H 78H Details of Setting Value Sets Y address 78H Sets an area of 120 lines
Setting A-3
Register Partial display area start line register (R20, R21) Partial display area line count register (R22, R23) Setting Value B4H 78H Details of Setting Value Sets Y address B4H Sets an area of 120 lines
Setting A-4
Register Partial display area start line register (R20, R21) Partial display area line count register (R22, R23) Setting Value 3CH 78H Details of Setting Value Sets Y address 3CH Sets an area of 120 lines
Data Sheet S15817EJ2V0DS
45
PD161623
Figure 5-27. Partial Display Setting Examples
Setting A-1
176 Gate 1
Source Gate 1 1
Source 1
Setting A-2
176
Partial display area
Area not displayed
120 121
120 121
Area not displayed
Partial display area
240
240
Source Gate 1 1
Setting A-3
176 Partial display area Gate
Source 1 1
Setting A-4
176 Area not displayed
60 61
60 61
Area not displayed
Partial display area
180 181 Partial display area 240
180 181 Area not displayed 240
46
Data Sheet S15817EJ2V0DS
PD161623
5.11 Screen Scroll The PD161623 has a screen scroll function. Any area of the screen can be scrolled by using the scroll area start line register (R15), scroll area line count register (R16), and scroll step count register (R17) to set the Y address of the top line of the area to be scrolled, the count of lines of the area to be scrolled, and the scroll step number, respectively. Note that in partial mode, the screen scroll function is disabled. Table 5-13. Scroll Area Start Line Register (R15)
SSL7 0 0 0 0 1 1 1 SSL6 0 0 0 0 0 0 0 SSL5 0 0 0 0 1 1 1 SSL4 0 0 0 0 0 0 0 SSL3 0 0 0 0 1 1 1 SSL2 0 0 0 0 1 1 1 SSL1 0 0 1 1 0 1 1 SSL0 0 1 0 1 1 0 1 Start Line Y Address 00H 01H 02H 03H EDH EEH EFH
Table 5-14. Scroll Area Line Count Register (R16)
SAW7 0 0 0 0 1 1 1 SAW6 0 0 0 0 0 0 0 SAW5 0 0 0 0 1 1 1 SAW4 0 0 0 0 0 0 0 SAW3 0 0 0 0 1 1 1 SAW2 0 0 0 0 1 1 1 SAW1 0 0 1 1 0 1 1 SAW0 0 1 0 1 1 0 1 Scroll Area Line Number 1 2 3 4 238 239 240
Table 5-15. Scroll Step Count Register (R17)
SST7 0 0 0 0 1 1 1 SST6 0 0 0 0 0 0 0 SST5 0 0 0 0 1 1 1 SST4 0 0 0 0 0 0 0 SST3 0 0 0 0 1 1 1 SST2 0 0 0 0 1 1 1 SST1 0 0 1 1 0 1 1 SST0 0 1 0 1 1 0 1 Scroll Step Number 0 (No scroll) 1 2 3 237 238 239
Scrolling must be set using the following sequence.
Data Sheet S15817EJ2V0DS
47
PD161623
(1) Recommended scroll sequence D7
SSLn setting
R15 D0 D7
<1> Scroll area start line setting
Note1
SAWn setting
R16 D0 D7
<2> Scroll area line count setting
Note1
SSTn setting
R17 D0
<3> Scroll step count register setting
Note2
Notes 1. <1> to <2> can be executed in any order. 2. <3> must be executed after <1> and <2> have been set. Remark Set SSTn to 00H to disable the scroll operation. No particular sequence is required for this. Cautions 1. If the sum of the values of SSLn and SAWn is 240 (EFH) or over, it is invalid (no scroll operation). 2. Set the step number SSTn so that it does not exceed the line number SAWn. If a value exceeding SAWn is set, it will be invalid (no scroll operation).
48
Data Sheet S15817EJ2V0DS
PD161623
(2) Scroll setting examples Setting A-1
Register Scroll area start line register (R15) Scroll area line count register (R16) Setting Value 00H EFH Details of Setting Value Sets Y address 00H Sets an area of 240 lines
Setting A-2
Register Scroll area start line register (R15) Scroll area line count register (R16) Setting Value 00H 77H Details of Setting Value Sets Y address 00H Sets an area of 120 lines
Setting A-3
Register Scroll area start line register (R15) Scroll area line count register (R16) Setting Value 78H 77H Details of Setting Value Sets Y address 78H Sets an area of 120 lines
Setting A-4
Register Scroll area start line register (R15) Scroll area line count register (R16) Setting Value B4H 77H Details of Setting Value Sets Y address B4H Sets an area of 120 lines
Data Sheet S15817EJ2V0DS
49
PD161623
Figure 5-28. Display Scroll Setting Examples
Setting A-1
176 Gate 1
Source Gate 1 1
Source 1
Setting A-2
176
Scroll area
Scroll area
120 121
Fixed display area
240
240
Source Gate 1 1
Setting A-3
176 Gate
Source 1 1
Setting A-4
176 Fixed display area
60 61 Fixed display area
120 121
Scroll area
Scroll area 180 181 Fixed display area 240 240
50
Data Sheet S15817EJ2V0DS
PD161623
(3) Scroll setting flowchart example
Start R15 Scroll area start line register setting R16 Scroll area line count register setting D15 D8 D7 D0 X 0 0 1 0 0 0 0 L D7 D6 D5 D4 D3 D2 D1 D0 Caution D7 to D0 are the data for Scroll area line count register.
RS RS
D15 D7 X 0 0 0 1 1 1 L D6 D5 D4 D3 D2 D1 D7 Caution D7 to D0 are the data for Scroll area start line.
D8 D0 1 D0
R17 Scroll step count register setting (1 step) R6 X address register setting
RS
L
D15 D7 X 0
0 0
0 0
1 0
0 0
0 0
0 0
D8 D0 1 1
RS
R7 Y address register setting
D15 D7 X 0 0 0 0 1 1 L D6 D5 D4 D3 D2 D1 D7 Caution D7 to D0 depend on application condition. D15 D7 X 0 0 0 0 1 1 L D6 D5 D4 D3 D2 D1 D7 Caution D7 to D0 depend on application condition. D15 D7 D15 D14 D13 D12 D11 D10 H D6 D5 D4 D3 D2 D7 Caution D15 to D0 are display memory data. D15 D7 D15 D14 D13 D12 D11 D10 H D6 D5 D4 D3 D2 D7 Caution D15 to D0 are display memory data.
D8 D0 0 D0
RS
D8 D0 1 D0
Display data Re-write scrolling area 1 (Start) Display data Re-write scrolling area 2
RS
D9 D1
D8 D0 D8 D0
RS
D9 D1
D8 D0 D8 D0
Display data Re-write scrolling area n (End)
RS
D15 D7 D15 D14 D13 D12 D11 D10 H D6 D5 D4 D3 D2 D7 Caution D15 to D0 are display memory data.
D9 D1
D8 D0 D8 D0
Data Sheet S15817EJ2V0DS
51
PD161623
R17 Scroll step count register setting (2 steps) R6 X address register setting
RS RS
L
D15 D7 X 0
0 0
0 0
1 0
0 0
0 0
1 0
D8 D0 0 1
R7 Y address register setting
D15 D7 X 0 0 0 0 1 1 L D7 D6 D5 D4 D3 D2 D1 Caution D7 to D0 depend on application condition. D15 D7 X 0 0 0 0 1 1 L D6 D5 D4 D3 D2 D1 D7 Caution D7 to D0 depend on application condition. D15 D7 D15 D7
D8 D0 0 D0
RS
D8 D0 1 D0
Display data Re-write scrolling area 1 (Start) Display data Re-write scrolling area 2 Display data Re-write scrolling area n (End) Next transaction
RS
H
D14 D6
D13 D5
D12 D4
D11 D3
D10 D2
D9 D1
D8 D0 D8 D0
Caution D15 to D0 are display memory data. D15 D7 D15 D7 D8 D0 D8 D0
RS
H
D14 D6
D13 D5
D12 D4
D11 D3
D10 D2
D9 D1
Caution D15 to D0 are display memory data.
RS
H
D15 D7 D15 D7
D14 D6
D13 D5
D12 D4
D11 D3
D10 D2
D9 D1
D8 D0 D8 D0
Caution D15 to D0 are display memory data. (Repeat)
52
Data Sheet S15817EJ2V0DS
PD161623
(4) Scroll function example Scroll area start line register (R15): 3CH Scroll area line count register (R16): 77H (a) Scroll step count register setting (R17): 00H
Source Gate 1 1 Fixed display area 60 61 3BH 3CH 176 Y address 00H
Scroll area
180 181 Fixed display area 240
B3H B4H
EFH
(b) Scroll step count register setting (R17): 01H
Source Gate 1 1 Fixed display area 60 61 3BH 3DH 176 Y address 00H
Scroll area
180 181 Fixed display area 240
B3H 3CH B4H
EFH
Data Sheet S15817EJ2V0DS
53
PD161623
(c) Scroll step count register setting (R17): 02H
Source Gate 1 1 Fixed display area 60 61 3BH 3EH 176 Y address 00H
Scroll area
180 181 Fixed display area 240
B3H 3CH 3DH B4H
EFH
(d) Scroll step count register setting (R17): 57H
Source Gate 1 1 Fixed display area 60 61 3BH B3H 3CH 176 Y address 00H
Scroll area
180 181 Fixed display area 240
B2H B4H
EFH
54
Data Sheet S15817EJ2V0DS
PD161623
5.12 Stand-by The PD161623 has a stand-by function. Input of a stand-by command is acknowledged when the STBY bit of the control register 1 (R0) is set to 1. When the stand-by command has been input, the PD161623 is forcibly placed in the VSS display status, and scans the frame being display to the end. When scanning is complete, all gate outputs are turned on, the charge of the pixel on the TFT panel is decreased to 0, and the output stage amplifier and internal oscillator are stopped. The stand-by function is valid for only the source driver IC; the gate IC ( PD161641) and power IC ( PD161660) connected to the PD161623 are not controlled by this function. After executing the stand-by command, therefore, execute commands that turn off the regulator for the gate IC and power IC an turn off the DC/DC converter. When the stand-by status is released, turn on the DC/DC converter and the regulator of the gate IC and power IC, and then issue an ordinary operation command (STBY = 0), in the reverse order to which the stand-by command was input. (1) Stand-by sequence
Operating status (normal display) R0 Control register 1 setting D15 to D0 Control register 1 D15 D8 RS D7 D0 0 0 0 0 0 0 0 0 L 1 X X D5 0 0 0 0 D7: Don't care D6: Don't care D4: Normal display mode (not partial display mode) D3: Stand-by ON D2: 65,000-color display mode D1: Normal power mode D5 is set in accordance with the usage conditions. The source output is automatically fixed to the VSS level by standby, so D7 and D6 can be set to any value. At least one frame period
Wait time 1 (tOE2RG) R25 Power supply control register 1 setting
Wait time 2 (tRPDD)
D15 to D0 Power supply control register 1 D15 D8 RS D7 D0 0 0 0 1 1 0 0 1 L 0 D5 D4 D3 X 1 X D6 D6 to D3 are set in accordance with the usage conditions. D1: Power supply IC regulator OFF D0: DC/DC converter ON Although a setting of 0 ns has no negative effect in terms of the device, be sure to finalize the timing after sufficient evaluation with the LCD module.
Data Sheet S15817EJ2V0DS
55
PD161623
R25 Power supply control register 1 setting D15 to D0 Power supply control register 1 D15 RS D7 0 0 0 1 1 0 0 L D5 D4 D3 X 0 X D6 D6 to D3 are set in accordance with the usage conditions. D2: Gate driver regulator OFF D1: Power supply IC regulator OFF D0: DC/DC converter OFF D8 D0 1 0
Stand-by setting completed
(2) Stand-by release sequence
Stand-by status R0 Control register 1 setting D7 to D0 Control register 1 D15 RS D7 X X X X X X L 1 0 0 D5 0 0 D7: All data "1" output (normally white: white output) D6: Normal display D4: Normal display mode (not partial display mode) D3: Normal mode (stand-by release) D2: 65,000-color display mode D1: Normal power mode D5 is set in accordance with the usage conditions. D8 D0 X 0
X 0
R25 Power supply control register 1 setting D15 to D0 Power supply control register 1 D15 D8 RS D7 D0 0 0 0 1 1 0 0 1 L 1 X D6 D5 D4 D3 X 0 D6 to D3 is set in accordance with the usage conditions. D1: Power supply IC regulator OFF D0: DC/DC converter ON tDDRP is the output stable period of the DC/DC converter. Although a setting of about 50 ms is the target, be sure to finalize the timing after sufficient evaluation with the LCD module. D7 to D0 Power supply control register 1 D15 D8 RS D7 D0 0 0 0 1 1 0 0 1 L 1 D5 D4 D3 0 1 X D6 D6 to D3 is set in accordance with the usage conditions. D1: Power supply IC regulator ON D0: DC/DC converter ON tRPRG is the output stable period of the DC/DC converter. Although a setting of about 20 ms is the target, be sure to finalize the timing after sufficient evaluation with the LCD module.
Wait time 1 (tDDRP) R25 Power supply control register 1 setting
Wait time 2 (tRPRG)
56
Data Sheet S15817EJ2V0DS
PD161623
R0 Control register 1 setting D7 to D0 Control register 1 D15 RS D7 0 0 0 0 0 0 0 L 0 0 0 0 0 0 D5 D7: Normal display (All data "1" output display ON) D6: Normal display D4: Normal display mode (not partial display mode) D3: Normal mode (stand-by release) D2: 65,000-color display mode D1: Normal power mode D5 is set in accordance with the usage conditions. D8 D0 0 0

Next transaction
Data Sheet S15817EJ2V0DS
57
PD161623
6 RESET
If the /RESET input becomes L or the reset command is input, the internal timing generator is initialized. The reset command will also initialize each register to its default value. These default values are listed in the table below.
Register Control register 1 Control register 2 Data supplement register Data access control register X address register Y address register MIN. X address register MAX. X address register MIN. Y address register MIN. Y address register Display size setting register Scroll area start line register Scroll area line count register Scroll step count register Partial off area color register Partial 1 display area start line register Partial 2 display area start line register Partial 1 display area line count register Partial 2 display area line count register Power supply control register 1 Power supply control register 2 VCOM output center value setting register Output stage capacity setting register Rn R0 R1 R4 R5 R6 R7 R8 R9 R10 R11 R13 R15 R16 R17 R19 R20 R21 R22 R23 R25 R26 R29 R30 R31 R36 R37 R38 R39 R40 R42 R45 R46 R49 R114 R115 /RESET Pin X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Note1
Reset Command O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O
Default Value A0H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 01H 06H 00H 00H 00H 00H
-reference-voltage generator capacity setting register -contrast value setting register 1 -contrast value setting register 2 -contrast value setting register 3 -contrast value setting register 4
5
Pre-charge direction setting data register
-correction input disconnect register
Calibration register
Note2
5
Pre-charge period supplement pulse setting register Output port register Interface operating voltage setting register Internal logic operating voltage setting register Test mode
Remark O: Default value set, X: Default value not set Notes 1. The internal counters are initialized only by a reset from the /RESET pin. Be sure to perform reset via the /RESET pin at power application. 2. The following value is set as the calibration setting time, tcal, in a reset by reset command. tcal = 1/fOSC x 37
58
Data Sheet S15817EJ2V0DS
PD161623
7. COMMAND
7.1 Command List Display data access
Data Bit RAM access RS R/W DB17 DB8 18-bit parallel interface Display data read 1 Display data write 1 1 1 1 0 D17 D8 D17 D8 Hi-Z D9 - D9 Hi-Z Display data read 3 1 1 D17 (D8) Hi-Z Display data write 3 Common Status Read 0 1 1 0 D17 (D8) D16 D7 D16 D7 Hi-Z D8 - D8 Hi-Z D16 (D7) Hi-Z D16 (D7) D15 D6 D15 D6 D17 D7 D17 D7 "0" D15 (D6) X D15 (D6) D14 D5 D14 D5 D16 D6 D16 D6 "0" D14 (D5) X D14 (D5) D13 D4 D13 D4 D15 D5 D15 D5 "0" D13 (D4) X D13 (D4) D12 D3 D12 D3 D14 D4 D14 D4 "0" D12 (D3) X D12 (D3) D11 D2 D11 D2 D13 D3 D13 D3 "0" D11 (D2) X D11 (D2) D10 D1 D10 D1 D11 D2 D11 D2 "0" D10 (D1) X D10 (D1) D9 D0 D9 D0 D10 D1 D10 D1 "0" D9 (D0) X D9 (D0) DB16 DB7 DB15 DB6 DB14 DB5 DB13 DB4 DB12 DB3 DB11 DB2 DB10 DB1 DB9 DB0
16-bit parallel interface (1-pixel/16-bit mode [DTX=L]) Display data read 2 Display data write 2 1 1 1 0
16-bit parallel interface (1-pixel / 18-bit mode [DTX=H])
Remark Hi-Z: High impedance, X: Invalid data Caution When the 16-bity parallel interface is used in 1-pixel/18-bit mode (DTX = H), data access of two words per pixel is required.
Data Sheet S15817EJ2V0DS
59
PD161623
18-bit parallel interface mode, DB17, DB16 = 0
Data Bit Rn Register RS R/W DB15 DB7 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 Control register 1 Control register 2 - Reset register Data supplement register Data access control register X address register Y address register MIN. X address register MAX. X address register MIN. Y address register MAX. Y address register - Display size setting register - Scroll area start line register Scroll area line count register Scroll step count register - Partial off area color register Partial 1 display area start line register Partial 2 display area start line register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DISP1
(1/3)
DB14 DB6 0
DISP0
DB13 DB5 0 ADC 0
VSEL
DB12 DB4 0 DTY 0
GSEL
DB11 DB3 0
STBY
DB10 DB2 0
COLOR
DB9 DB1 0 LPM 0 LTS 1 1 0
CD12
DB8 DB0 0 GSM 1 INV 0 1 RES 0
CD0
0 0 0 0 0 0 XA7 0 YA7 0
XMIN7
0 0 0 0 0
BSTR
0 0 0 0 0 0 0 XA3 0 YA3 1
XMIN3
0 0 0 0 1 1 0 1 XA2 1 YA2 0
XMIN2
0 0 0 0 0 XA5 0 YA5 0
XMIN5
0 0 0 0 WAS 0 XA4 0 YA4 0
XMIN4
0 0 1 XA1 1 YA1 0
XMIN1
1 0 0 XA0 1 YA0 0
XMIN0
0 XA6 0 YA6 0
XMIN6
0
XMAX7
0
XMAX6
0
XMAX5
0
XMAX4
1
XMAX3
0
XMAX2
0
XMAX1
1
XMAX0
0
YMIN7
0
YMIN6
0
YMIN5
0
YMIN4
1
YMIN3
0
YMIN2
1
YMIN1
0
YMIN0
0
YMAX7
0
YMAX6
0
YMAX5
0
YMAX4
1
YMAX3
0
YMAX2
1
YMAX1
1
YMAX0
0 0 0 0 SSL7 0
SAW7
0 0 0 0 SSL6 0
SAW6
0 0 0 0 SSL5 0
SAW5
0 0 0 0 SSL4 1
SAW4
1 1 1 1 SSL3 0
SAW3
1 1 1 1 SSL2 0
SAW2
0 0 1 1 SSL1 0
SAW1
0 1
NGO0
0 1 SSL0 0
SAW0
0 SST7 0 0 0
P1SL7
0 SST6 0 0 0
P1SL6
0 SST5 0 0 0
P1SL5
1 SST4 1 1 1
P1SL4
0 SST3 0 0 0
P1SL3
0 SST2 0 0 PGR 1
P1SL2
0 SST1 1 1 PGG 0
P1SL1
1 SST0 0 1 PGB 0
P1SL0
0
P2SL7
0
P2SL6
0
P2SL5
1
P2SL4
0
P2SL3
1
P2SL2
0
P2SL1
1
P2SL0
60
Data Sheet S15817EJ2V0DS
PD161623
18-bit parallel interface mode, DB17, DB16 = 0
Data Bit Rn Register Partial 1 display area line count register Partial 2 display area line count register - Power supply control register 1 Power supply control register 2 - - VCOM output center value setting register Output stage capacity setting register RS R/W DB15 DB7 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
P1AW7
(2/3)
DB14 DB6 0
P1AW6
DB13 DB5 0
P1AW5
DB12 DB4 1
P1AW4
DB11 DB3 0
P1AW3
DB10 DB2 1
P1AW2
DB9 DB1 1
P1AW1
DB8 DB0 0
P1AW0
0
P2AW7
0
P2AW6
0
P2AW5
1
P2AW4
0
P2AW3
1
P2AW2
1
P2AW1
1
P2AW0
0 0 0 0 0 0 EV7 0 BPL 0 WHP 0 0 0 0 0
GPH7
0 0
BGRS
0 0
VCE
1 1
VCD2
1 1
PVCOM
0 0 0 0 1 1 EV2 1 SF2 1 BI2 0 0 0 0 1
GPH2
0 0
RGONP
0 1
DCON
0 0 0 0 EV6 0 CI2 0 WI2 0 0 0 0 0
GPH6
0 0 0 0 EV5 0 CI1 0 WI1 1 1 1 1 1
GPH5
1 1 1 1 EV4 1 CI0 1 WI0 0 0 0 0 0
GPH4
1 1 1 1 EV3 1
VCOMC
1
VCD12
0
VCD11
1 0 0 EV1 1 SF1 1 BI1 0 0 1 1 0
GPH1
1 0 1 EV0 0 SF0 1 BI0 0 1 0 1 0
GPH0
-reference-voltage generator
capacity setting register - - - -
-contrast value setting register 1 -contrast value setting register 2 -contrast value setting register 3 -contrast value setting register 4
1 BHP 0 0 0 0 0
GPH3
0
GNH7
0
GNH6
1
GNH5
0
GNH4
0
GNH3
1
GNH2
0
GNH1
1
GNH0
0 GPL7 0 GNL7 0
RDTP3
0 GPL6 0 GNL6 0
RDTP2
1 GPL5 1 GNL5 1
RDTP1
0 GPL4 0 GNL4 0
RDTP0
0 GPL3 0 GNL3 1
RDTN3
1 GPL2 1 GNL2 0
RDTN2
1 GPL1 1 GNL1 0
RDTN1
0 GPL0 1 GNL0 0
RDTN0
Pre-charge direction setting data register -
-correction input disconnect register
0 0 0
0 0 0
1 1 1
0 0 0
1 1 1
0 0 0
0 1 1
1 0
GHSW
-
1
Data Sheet S15817EJ2V0DS
61
PD161623
18-bit parallel interface mode, DB17, DB16 = 0
Data Bit Rn Register RS R/W DB15 DB7 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R114 R115 - Calibration register Pre-charge period supplement pulse setting register - - Output port register - - - - - - - - - - - - - - Interface operating voltage setting register Internal logic operating voltage setting register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OP7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB14 DB6 0 0 0
PLIM6
(3/3)
DB13 DB5 1 1 1
PLIM5
DB12 DB4 0 0 0
PLIM4
DB11 DB3 1 1 1
PLIM3
DB10 DB2 1 1 1
PLIM2
DB9 DB1 0 0 1
PLIM1
DB8 DB0 0 1 OC 0
PLIM0
0 0 0 OP6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
1 1 1 OP5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 OP4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 OP3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0
1 0 0 OP2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
1 0 0 OP1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1
RTSC1
1 0 1 OP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
RTSC0
1
RTSL1
1
RTSL0
62
Data Sheet S15817EJ2V0DS
PD161623
7.2 Command Explanation (1/8)
Register R0 D7 Bit Symbol DISP1 Function This command performs the same output as when all data is 1, independently of the internal RAM data (white display in the case of normally white). This command is executed, after it has been transferred, when the next line isoutput. 0: Normal operation 1: Ignores data of RAM and outputs all data as 1. DISP1 takes precedence over DISP0. When DISP1 = H, DISP0 = H is ignored. D6 DISP0 This command performs the same output as when all data is 0, independently of the internal RAM data (black display in the case of normally white). This command is executed, after it has been transferred, when the next line is output. 0: Normal operation 1: Ignores data of RAM and outputs all data as 0. D5 ADC Column address direction This command can be used to select the direction of source driver output. For more detail, refer to 5.2.3 Column address circuit. D4 DTY This pin selects the partial function. When the partial function s selected in the 260,000-color mode, set the partial-OFF area-color selection register (R27) to 00H. In the 8-color mode, the partial OFF area color can be set to any value from 00H to 07 H. The power consumption cannot be reduced with the partial function. To reduce the power consumption, select the 8-color mode. This command is executed following transfer from the time the next line data is output. 0: Normal display mode 1: Partial display mode
5
D3
STBY
This bit selects the stand-by function. When the stand-by function is selected, a display OFF operation is executed and the amplifiers at each output stage and the operation of internal oscillation circuit are stopped. However, stand-by control cannot be performed for the power supply ICs ( PD161660 and others) connected to PD161623. Therefore, after executing the stand-by function using this bit, set both the regulator for the power supply IC to off and set the DC/DC converter to OFF. For the sequence, refer to the data sheets of the power supply IC. Note that when releasing stand-by, perform the opposite operation, i.e., after setting the DC/DC converter to ON and setting the regulators of the power supply IC to ON, execute the normal operation command. 0: Normal operation 1: Stand-by function (Display read off from RAM, stop both OSC and VCOM, display off = entire data is output as 1)
D2
COLOR
This pin switches the 260,000-color mode and the 8-color mode. When the 8-color mode is selected, low power supply can be selected in order to stop the amplifier at each output stage. In the 8-color mode, the value of the MSB of the internal RAM data is used as the color data. This command is executed following transfer from the time the next line data is output. 0: 260,000-color mode (18-bits/pixels) 1: 8-color mode (3-bits/pixels)
Data Sheet S15817EJ2V0DS
63
PD161623
(2/8)
Register R0 D1 Bit Symbol LPM Function This bit is used when setting the power supply IC ( PD161660) to the low-power mode. When the low-power mode is selected, the LPMP pin signal change from low to high (output changes immediately following command execution.). The LPMP pin must be connected to the LPM pin of the power supply IC. 0: Normal 1: Low power mode Sets output of the gate scanning signal during partial display. When 1 is selected, gate scanning of the line set in the partial non-display area is stopped. 0: Normal mode 1: Stops gate scanning in partial non-display area Sets the potential of the pre-charge output of the LCD driver. The maximum/minimum output potential of the pre-charge output is: 0: Maximum output level of internal -output adjustment circuit (uses VPH, VNH, VPL, VNL) 1: Partial voltage (outputs VS and VSS) IF VSEL = 0, VS or VSS is automatically output as the pre-charge output. Sets the maximum/minimum output voltage of the -correction register. If the internal -output adjustment circuit is selected, the maximum/minimum output potential of the -correction register is: 0: Supply voltage (outputs VS and VSS). 1: Voltage of internal -output adjustment circuit (uses VPH, VNH, VPL, VNL) 8-color mode (3 bits/pixels) Selects set time of calibration. The calibration function adjusts the frame frequency by setting time of one line. This command can select the set time of a line from the following: 0: 1 line time = tcal 1: 1 line time = tcal x 2 (tcal: Calibration set time1 = 1 / Frame frequency / Number of displayed lines) This bit selects between the line inversion function and the frame inversion function. The mode selected by this command is executed from the start of the next scan after the gate scan in progress when this command was executed has completed 176 lines. 0: Line inversion 1: Frame inversion Command reset function. Be sure to execute this bit after power ON. Command reset automatically clears this bit following execution (RES = 1). Therefore, it is not necessary to set 0 (select normal operation) again by software. Moreover, since the time required for the value of this bit to change (1 0) following command reset execution is extremely short, it is not necessary to secure time until the next command is set following command reset setting. 0: Normal operation 1: Command reset When using the 1-pixel/16-bit mode (DTX = L) and the 18-bit parallel interface, when the data from the CPU is stored in the display RAM, this register supplements data (display RAM data: D12, D0) for the two bits of deficient data using the set data and writes 18-bit data to the display RAM. For details, refer to 5.1.2 Selection of data transfer mode. CD12: Display RAM data D12 is supplemented CD0: Display RAM data D0 is supplemented
D0
GSM
R1
D5
VSEL
D4
GSEL
D1
LTS
D0
INV
R3
D0
RES
R4
D1
CD12
D0
CD0
64
Data Sheet S15817EJ2V0DS
PD161623
(3/8)
Register R5 D6 Bit Symbol BSTR Function Sets the write mode for writing data to the display RAM. If the high-speed RAM write mode is selected, data is written to the display RAM in 2-pixel units inside the PD161623. When selecting the high-speed RAM write mode, be sure to write data to the display RAM in 2-pixel units. 0: Normal write mode (18-bit access: 4 MHz MAX.) 1: High-speed RAM write mode (36-bit access: 8 MHz MAX.) Window access mode setting When the window access mode is set, the address is incremented/decremented only in the range set by the MIN. X address setting register (R8), MAX. X address setting register (R9), MIN. Y address setting register (R10), and MAX. Y address setting register (R11). 0: Normal operation 1: Window access mode This register sets the X address of the display RAM. Set a value between 00H and AFH. This register sets the Y address of the display RAM. Set a value between 00H and EFH. Sets the minimum value of the X address in the window access mode. The X address is incremented up to the maximum value set by the MAX. X address register (R9), and then initialized to the address value set by this command. Set this register to 00H to AEH. Sets the maximum value of the X address in the window access mode. The X address is incremented up to the maximum value set by the MIN. X address register (R8), and then initialized to the address value set by this command. Set this register to 01H to AFH. Sets the minimum value of the T address in the window access mode. The Y address is incremented up to the maximum value set by the MAX. Y address register (R11), and then initialized to the address value set by this command. Set 00H to EEH. Sets the maximum value of the Y address in the window access mode. The Y address is incremented up to the address value set by this command, and then initialized to the minimum address value set by the MIN. Y address register (R10). Set 01H to EFH. Selects output number (gate scan) of gate driver.
NGO0 0 1 Gate Output Number 240-gate outputs 220-gate outputs
D4
WAS
R6 R7 R8
D7 to D0 D7 to D0 D7 to D0
XAn YAn XMINn
R9
D7 to D0
XMAXn
R10
D7 to D0
YMINn
R11
D7 to D0
YMAXn
R13
D0
NGO0
R15
D7 to D0
SSLn
Scroll area start line register (00H to EFH) When the screen is scrolled, the screen of the number of lines set by the scroll area line count register (R16) is scrolled up by the number of steps set by the scroll step count register (R17), starting from the line set by this command.
R16
D7 to D0
SAWn
Scroll area line count register (00H to EFH) When the screen is scrolled, the screen of the number of lines set by this command is scrolled up by the number of steps set by the scroll step count register (R17), starting from the line set by the scroll area start line register (R15).
Data Sheet S15817EJ2V0DS
65
PD161623
(4/8)
Register R17 Bit D7 to D0 Symbol SSTn Scroll step count register (00H to EFH) When the screen is scrolled, the screen of the number of lines set by the scroll area line count register (R16) and the scroll step count register (R17) is scrolled up by the number of steps set by this command. Note that because this command is invalid in the partial display mode, the scroll function cannot be used. R19 D2 PGR Partial off area color register Sets the color of the screen other than the partial display area during partial display (R0: DTY = 1). One of eight colors can be selected (RGB: 1 bit each) as the off color. D1 PGG The relationship between each color data and the bits of this register is as follows. This relationship is not dependent upon the value of ADC. D0 PGB PGR: R OFF= 0, ON = 1 PGG: G OFF= 0, ON = 1 PGB: B OFF= 0, ON = 1 R20 D7 to D0 P1SLn Partial1 display area start line register (00H to EFH) During partial display (R0: DTY = 1), the area starting from the line set by this command and ending as set by the partial 1 display area line count register (R22) is the partial 1 display area. R21 D7 to D0 P2SLn Partial2 display area start line register (00H to EFH) During partial display (R0: DTY = 1), the area starting from the line set by this command and ending as set by the partial 2 display area line count register (R23) is the partial 2 display area. R22 D7 to D0 P1AWn Partial1 display area line count register (00H to EFH) An area starting from the line set by the partial 1 display area start register (R20) and ending as set by this command is the partial 1 display area. If this register is 0, the values of the partial 2 display area start line register (R29) and the partial 2 display area line count register (R31) are not valid. R23 D7 to D0 P2AWn Partial 2 display area line count register (00H to EFH) An area starting from the line set by the partial 2 display area start register (R21) and ending as set by this command is the partial 2 display area. If the partial 1 display area line count register is 0, the values of the partial 2 display area start line register (R21) and partial 2 display area line count register (R23) are not valid. R25 D6 BGRS This pin selects whether to use the internal power supply or an external power supply (input from the BRGIN pin) for generation the common center voltage output from the VCOM pin. 0: The internal power supply is selected as the VCOM power supply 1: Input from the external power supply BGRIN is selected as the BCOM power supply D5 VCE Selects the VO output level of the power supply IC ( PD161660). The VCE pin of the PD161623 and the VCE pin of the power supply IC must be connected. 0: The Vo high-level booster voltage level is VDD2 minus 1 level 1: The Vo high-level booster voltage level is the same level as VDD2 D4 VCD2 Selects the VDD2 output level of the power supply IC ( PD161660). The VCD2 pin of the PD161623 and the VCD2 pin of the power supply IC must be connected. 0: VDD2 = VCD x 2 1: VDD2 = VCD x 3 D3 PVCOM Selects the voltage supplied to the VCOM output circuit. 0: VCOM output circuit power supply, VDD2 1: VCOM output circuit power supply, VS Function
66
Data Sheet S15817EJ2V0DS
PD161623
(5/8)
Register R25 D1 Bit Symbol RGONP Function Switches the internal DC/DC converter of the power supply IC ( PD161660) ON/OFF. When OFF is selected, a low level is output from the RGONP pin, and when ON is selected, a high level is output from the RGONP pin. The RGONP pin of this IC and the RGONP pin of the power supply IC must be connected. 0: Regulators of power supply IC (VT, VS) are OFF 1: Regulators of power supply IC (VT, VS) are ON D0 DCON Switches the internal DC/DC converter of the power supply IC ( PD161660) ON/OFF. When OFF is selected, a low level is output from the DCON pin, and when ON is selected, a high level is output from the DCON pin. The DCON pin of the PD161623 and the DCONP pin of the power supply IC must be connected. 0: DC/DC converter is OFF 1: DC/DC converter is ON R26 D1 VCD12 Performs booster control for the DC/DC converter in the power supply IC ( PD161660) The data set with this bit is output from the VCD11 pin and the VCD12 pin. The VCD11 pin and VCD12 pin of the PD161623 must be connected to the VCD11 pin and the VCD12 pin of the power supply IC. D0 VCD11 VCD12, VCD11 = 0, 0: VDD2 = VDC x 4 = 0, 1: VDD2 = VDC x 5 = 1, 0: VDD2 = VDC x 6 = 1, 1: VDD2 = VDC x 7 R29 D7 to D0 EVn Sets the D/A converter circuit used to adjust the voltage of the reference voltage generator circuit (VBGR) input to the voltage regulator that sets the center value of the panel common drive output. The D/A converter divides the constant voltage generated by the reference voltage generator (VBGR) by 256, and one level can be selected between VBGR and VSS by setting this command. For more detail, refer to 5.5 Common Adjustment Circuit and 5.8 D/A Converter Circuit. R30 D7 BPL Switched the capacity of the -correction circuit reference voltage generation amplifiers on the side not being used (VPH, VPL, VNH, VNL) to the minimum value based on the polarity inversion timing in order to reduce the current consumption. Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used. 0: Normal 1: Reference voltage generation amplifier capacity switch drive D6 to D4 CIn Sets the bias current of the amplifier for setting the panel's COMMON drive waveform center value (VCOM), as shown in the table below. Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used.
CI2 0 0 0 0 1 1 1 1 CI1 0 0 1 1 0 0 1 1 CI0 0 1 0 1 0 1 0 1 VCOM Center Value Setting Amplifier Bias Current Value 0.20 A 0.50 A 0.10 A 0.05 A 1.00 A 1.50 A 2.00 A 3.00 A
Data Sheet S15817EJ2V0DS
67
PD161623
(6/8)
Register R30 D3 Bit Symbol VCOMC value (VCOM) or not. This amplifier can be used under conditions such as when an external COMMON drive circuit is being used. 0: VCOM amplifier operating 1: VCOM amplifier stopped D2 to D0 SFn Sets the capacity of the source output (Y1 to Y528), as shown in the table below. Determine the output capacity after sufficient evaluation with the actual TFT panel to be used.
SF2 0 0 0 0 1 1 1 1 SF1 0 0 1 1 0 0 1 1 SF0 0 1 0 1 0 1 0 1 Source Output Bias Current Value 0.20 A 0.15 A 0.25 A 0.10 A 0.20 A 0.30 A 0.40 A 0.05 A
Function Selects whether to use the amplifier for setting the panel's COMMON drive waveform center
R31
D7
WHP
Sets the output mode of the reference voltage generator amplifier for setting the white level of the positive-polarity and negative-polarity sides (when VPL and VNL are normally white), as shown below. Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used. 0: Normal mode 1: High-power mode (output stage capacity: twice that of normal mode) Sets the output bias current of the reference voltage generator amplifier for setting the white level of the positive-polarity and negative-polarity sides (when VPL and VNL are normally white), as shown below.
WI2 0 0 0 0 1 1 1 1 WI1 0 0 1 1 0 0 1 1 WI0 0 1 0 1 0 1 0 1 0.20 A 0.50 A 0.10 A 0.05 A 1.00 A 1.50 A 2.00 A 3.00 A Amplifier Bias Current
D6 to D4
WIn
D3
BHP
Sets the output mode of the reference voltage generator amplifier for setting the black level of the positive-polarity and negative-polarity sides (when VPH and VNH are normally white), as shown below. Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used. 0: Normal mode 1: High-power mode (output stage capacity: twice that of normal mode)
68
Data Sheet S15817EJ2V0DS
PD161623
(7/8)
Register R31 Bit D2 to D0 Symbol BIn Function Sets the output bias current of the reference voltage generator amplifier for setting the black level of the positive-polarity and negative-polarity sides (when VPH and VNH are normally white), as shown below. Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used.
BI2 0 0 0 0 1 1 1 1 BI1 0 0 1 1 0 0 1 1 BI0 0 1 0 1 0 1 0 1 0.20 A 0.50 A 0.10 A 0.05 A 1.00 A 1.50 A 2.00 A 3.00 A Amplifier Bias Current
R36 R37 R38 R39 R40
D7 to D0 D7 to D0 D7 to D0 D7 to D0 D7 to D4
GPHn GNHn GPLn GNLn RDTPn
Sets the voltage value of the black level of positive polarity. For more detail, refer to 5.9 -Curve Correction Power Supply Circuit. Sets the voltage value of the white level of negative polarity. For more detail, refer to 5.9 -Curve Correction Power Supply Circuit. Sets the voltage value of the white level of positive polarity. For more detail, refer to 5.9 -Curve Correction Power Supply Circuit. Sets the voltage value of the white level of positive polarity. For more detail, refer to 5.9 -Curve Correction Power Supply Circuit. Sets the data value at which the pre-charge direction is switched during positive-polarity drive. The value set to RDTPn corresponds to the higher 4bits of display RAM data DBn (6 bits for each of RFB), as shown below.
RDTP3 Dot 1 (R) Dot 2 (G) Dot 3 (B) D17 D11 D5 RDTP2 D16 D10 D4 RDTP1 D15 D9 D3 RDTP0 D14 D8 D2
D3 to D0
RDTNn
Sets the data value at which the pre-charge direction is switched during negative-polarity drive. The value set to RDTNn corresponds to the higher 4 bits of display RAM data DBn (6 bits for each of RGB), as shown below.
RDTN3 Dot 1 (R) Dot 2 (G) Dot 3 (B) D17 D11 D5 RDTN2 D16 D10 D4 RDTN1 D15 D9 D3 RDTN0 D14 D8 D2
R42
D0
GHSW
Controls the -correction voltage input pins (V0 to V5) and the switch for connecting the PD161623 internal -correction resistor. 0: Switch OFF (disconnected) 1: Switch ON (connected)
R45
D0
OC
This bit is used for calibration. The time from calibration start command execution until calibration stop command execution becomes the time for 1 line. 0: Calibration stop 1: Calibration start
Data Sheet S15817EJ2V0DS
69
PD161623
(8/8)
Register R46 Bit D6 to D0 Symbol PLIMn Function Sets the clock count for the pre-charge period. The value written to this register is set as the clock count (1/fOCS) of the pre-charge period. For details, refer to 5.4.1 Dispaly timing R49 D7 to D0 OPn Output port (OP7 to OP0) write When after the output port register is specified in the index register, writing to the output port register is performed, the values written to the OP7 to OP0 pins are output.
5
R114
D1, D0
RTSCn
Selects the optimum internal circuit operation based on the operating voltage of the interface circuits. To set by this register, we recommend as follow setting.
RTSC1 0
RTSC0 1
Caution Always set this register and internal logic operating voltage setting register (R115) to the same value.
5
R115
D1, D0
RTSLn
Selects the optimum internal circuit operation based on the operating voltage of the internal logic circuits. To set by this register, we recommend as follow setting.
RTSC1 0 RTSC0 1
Caution Always set this register and interface operating voltage setting register (R114) to the same value.
70
Data Sheet S15817EJ2V0DS
PD161623
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS = 0 V)
Parameter Power supply voltage Power supply voltage Power supply voltage Power supply voltage for -curve correction Input voltage Input current Operating ambient temperature Storage temperature VS VDD1 VDD2 V0 to V5 VI II TA Tstg Symbol Ratings -0.5 to +6.5 -0.5 to VDD2 + 0.5 -0.5 to +4.0 -0.5 to VS + 0.5 -0.5 to VDD2 + 0.5 10 -40 to +85 -55 to +125 Unit V V V V V mA C C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = -40 to +85C, VSS = 0 V)
Parameter Power supply voltage VS VDD1 VDD2 Input voltage VI1 VI2
Note1 Note2
Symbol
MIN. 4.3 1.7 2.5 0 0
TYP. 5.0 1.8 2.7
MAX. 5.5 VDD2 3.6 VDD2 VDD1
Unit V V V V V
Notes 1. Pins of VDD1 power supply system: PSX, C86, TOUT0 to TOUT17, OP0 to OP7, LPMP, GOE1, GOE2, GSTB, GCLK, DCON, RGONP, VCD11, VCD12, VCD2, VCE, OSCSEL, TESTIN, TSTRTST, TSTVIHL, TOSCI 2. Pins of VDD2 power supply system: /CS, /RD (E), /WR (R,/W), D0 to D17, RS, /RESET, OSCIN
Data Sheet S15817EJ2V0DS
71
PD161623
Electrical Specifications (Unless Otherwise Specified, TA = -40 to +85C, VDD1 = 1.7 V to VDD2, VDD2 = 2.5 to 3.6 V, VS = 4.3 to 5.5 V)
Parameter Symbol VDD2 VDD1 VDD2 VDD1 VDD2, IOUT = -100 A VDD1, IOUT = -1 mA VCOUT1, VCOUT2, IOUT = -100 A VDD2, IOUT = 100 A VDD1, IOUT = 1 mA VCOUT1, VCOUT2, IOUT = 100 A ISOURCE = 100 A ISINK = -100 A Except D0 to D17 Except D0 to D17 D0 to D17 D0 to D17 VX = 3.5 V, VOUT = 4.5 V, VS = 5.0 V IVOL VCOM VDD1 (when non-access CPU) VDD2 (when non-access CPU) Stand-by mode, VDD2 pin 260,000-color mode 8-color mode Driver output Current (pre-charge) IVOL VO1 VO2 IVOH
Note3 Note3 Note2
Condition MIN.
Specification TYP.
Note1
Unit MAX. V V 0.2 VDD2 0.2 VDD1 V V V V V 0.1 VDD2 0.2 VDD1 0.1 VS V V V V VCOM - 0.3 1 -1 10 -10 -100 V
High level input voltage
VIH1 VIH2
0.8 VDD2 0.8 VDD1
Low level input voltage
VIL1 VIL2
High level output voltage
VOH1 VOH2 VOH3
0.9 VDD2 0.8 VDD1 0.9 V
Low level output voltage
VOL1 VOL2 VOL3
VCOM output voltage
VCOMH VCOML
VCOM - 0.3
High level input current Low level input current High level leakage current Low level leakage current High level driver output current Low level driver output current VCOM common output voltage fluctuation parameter Current consumption
IIH1 IIL1 ILIH ILIL IVOH
A A A A A A
VX = 2.0 V, VOUT = 1.0 V, VS = 5.0 V
Note2
150 -10
10
%
IDD1 IDD2 ISTBY
0.1 200 0.1 650 50
2 350 10 1250 200 -5
A A A A A A A
5
IS
VOUT = VS - 0.1 V, VS = 5.0 V
Note2
VOUT = VSS + 0.1 V, VS = 5.0 V
Note2
2
Output voltage deviation
VO = 1.3 V to VS - 1.3 V VO = 0.3 to 1.3 V VO = VS - 1.3 V to VS - 0.3 V
-20 -30
+20 +20
mV mV
Output voltage period
VO
Input data: H to H
VSS + 0.2
VS - 0.2
V
Notes 1. TYP. values are reference values when TA = 25C 2. VX refers to the output voltage of analog output pins Y1 to Y528. VOUT refers to the voltage applied to analog output pins Y1 to Y528. 5 72 3. Frame frequency: 60 Hz, line inversion mode select, dot checkerboard input pattern, no load.
Data Sheet S15817EJ2V0DS
PD161623
Switching characteristics (Unless Otherwise Specified, TA = -40 to +85C, VDD1 = 1.7 V to VDD2, VDD2 = 2.5 to 3.6 V, VS = 4.3 to 5.5 V)
Pre-charge period tPLH1 Driver output period tPHL2
VO MAX. -200 mV
Goal voltage +T.B.D. mV Goal voltage +T.B.D. mV
VOUT
VO MIN. +200 mV
tPHL1 tPLH2
Parameter Driver output delay time 1 (pre-charge period) Driver output delay time 2 (driver output period)
Symbol tPLH1 tPHL1 tPLH2 tPHL2 VS = 5.0 V, 4 k +27 pF
Condition VO MAX. -200 mV VO MIN. +200 mV Pre-charge completed goal voltage
MIN.
TYP.
Note
MAX. 7.0 9.5 50 52
Unit
s s s s
Note TYP. values are reference values when TA = 25C.
Data Sheet S15817EJ2V0DS
73
PD161623
AC Characteristics (Unless Otherwise Specified, TA = -40 to +85C, VDD1 = 1.7 V to VDD2, VDD2 = 2.5 to 3.6 V, VS = 4.3 to 5.5 V) (a) i80 series CPU interface
RS tAS8 tf tr tAH8
/CS tCYC8 tCCLW, tCCLR
/WR, /RD tCCHR, tCCHW tDS8 D0 to D17 (Write) tACC8 D0 to D17 (Read) tOH8 tDH8
74
Data Sheet S15817EJ2V0DS
PD161623
When VDD1 = 2.5 to 3.6 V, VDD2 = 2.5 to 3.6 V, VDD2 VDD1 (normal write mode, R114 = R115 = 01H)
Parameter Address hold time Address setup time System cycle time Control low-level pulse width (/WR) Control low-level pulse width (/RD) Control high-level pulse width (/WR) Control high-level pulse width (/RD) Data setup time Data hold time /RD access time Output disable time Symbol tAH8 tAS8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 /WR /RD /WR /RD D0 to D17 D0 to D17 D0 to D17, CL = 100 pF D0 to D17, CL = 100 pF 10 RS RS Condition MIN. 0 0 250 120 140 60 80 80 0 110 100 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
Note TYP. values are reference values when TA = 25C. Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VDD1. When VDD1 = 1.7 to 2.5 V, VDD2 = 2.5 to 3.6 V, VDD2 VDD1 (normal write mode, R114 = R115 = 01H)
Parameter Address hold time Address setup time System cycle time Control low-level pulse width (/WR) Control low-level pulse width (/RD) Control high-level pulse width (/WR) Control high-level pulse width (/RD) Data setup time Data hold time /RD access time Output disable time Symbol tAH8 tAS8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 /WR /RD /WR /RD D0 to D17 D0 to D17 D0 to D17, CL = 100 pF D0 to D17, CL = 100 pF 10 RS RS Condition MIN. 0 0 333 120 160 100 140 100 0 150 150 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
Note TYP. values are reference values when TA = 25C. Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VDD1.
Data Sheet S15817EJ2V0DS
75
PD161623
When VDD1 = 2.5 to 3.6 V, VDD2 = 2.5 to 3.6 V, VDD2 VDD1 (high-speed RAM write mode, valid only for writing data, R114 = R115 = 01H)
Parameter Address hold time Address setup time System cycle time Control low-level pulse width (/WR) Control high-level pulse width (/WR) Data setup time Data hold time Symbol tAH8 tAS8 tCYC8 tCCLW tCCHW tDS8 tDH8 /WR /WR D0 to D17 D0 to D17 RS RS Condition MIN. 0 0 125 60 30 80 0 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns
Note TYP. values are reference values when TA = 25C. Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VDD1. When VDD1 = 1.7 to 2.5 V, VDD2 = 2.5 to 3.6 V, VDD2 VDD1, (high-speed RAM write mode, valid only for writing data, R114 = R115 = 01H)
Parameter Address hold time Address setup time System cycle time Control low-level pulse width (/WR) Control high-level pulse width (/WR) Data setup time Data hold time Symbol tAH8 tAS8 tCYC8 tCCLW tCCHW tDS8 tDH8 /WR /WR D0 to D17 D0 to D17 RS RS Condition MIN. 0 0 167 60 50 100 0 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns
Note TYP. values are reference values when TA = 25C. Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VDD1.
76
Data Sheet S15817EJ2V0DS
PD161623
(b) M68 series CPU interface
RS tAS6 tf tr tAH6
/CS tCYC6 tEWHR, tEWHW
E tEWLR, tEWLW tDS6 tDH6
D0 to D17 (Write) tACC6 D0 to D17 (Read) tOH6
Data Sheet S15817EJ2V0DS
77
PD161623
When VDD1 = 2.5 to 3.6 V, VDD2 = 2.5 to 3.6 V, VDD2 VDD1 (normal mode, R114 = R115 = 01H)
Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable high pulse width Enable low pulse width Read Write Read Write Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW D0 to D17 D0 to D17 D0 to D17, CL = 100 pF D0 to D17, CL = 100 pF E E E E 10 140 120 80 60 RS RS Condition MIN. 0 0 250 80 0 110 100 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
Note TYP. values are reference values when TA = 25C. Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system cycle time, the rated value range is either (tr + tf) < (tCYC6-tEWLR-tEWHR) or (tr + tf) < (tCYC6-tEWLW-tEWHW). 2. All timing is rated based on 20 to 80% of VDD1. When VDD1 = 1.7 to 2.5 V, VDD2 = 2.5 to 3.6 V, VDD2 VDD1 (normal mode, R114 = R115 = 01H)
Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable high pulse width Enable low pulse width Read Write Read Write Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW D0 to D17 D0 to D17 D0 to D17, CL = 100 pF D0 to D17, CL = 100 pF E E E E 10 160 160 140 100 RS RS Condition MIN. 0 0 333 100 0 150 150 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
Note TYP. values are reference values when TA = 25C. Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system cycle time, the rated value range is either (tr + tf) < (tCYC6-tEWLR-tEWHR) or (tr + tf) < (tCYC6-tEWLW-tEWHW). 2. All timing is rated based on 20 to 80% of VDD1.
78
Data Sheet S15817EJ2V0DS
PD161623
When VDD1 = 2.5 to 3.6 V, VDD2 = 2.5 to 3.6 V, VDD2 VDD1 (high-speed RAM write mode, valid only for writing data, R114 = R115 = 01H)
Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Enable high pulse width Enable low pulse width Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tEWHR tEWLR D0 to D17 D0 to D17 E E RS RS Condition MIN. 0 0 125 80 0 60 30 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns
Note TYP. values are reference values when TA = 25C. Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system cycle time, the rated value range is either (tr + tf) < (tCYC6-tEWLR-tEWHR) or (tr + tf) < (tCYC6-tEWLW-tEWHW). 2. All timing is rated based on 20 to 80% of VDD1. When VDD1 = 1.7 to 2.5 V, VDD2 = 2.5 to 3.6 V, VDD2 VDD1 (high-speed RAM write mode, valid only for writing data, R114 = R115 = 01H)
Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Enable high pulse width Enable low pulse width Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tEWHR tEWLR D0 to D17 D0 to D17 E E RS RS Condition MIN. 0 0 167 100 0 60 50 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns
Note TYP. values are reference values when TA = 25C. Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system cycle time, the rated value range is either (tr + tf) < (tCYC6-tEWLR-tEWHR) or (tr + tf) < (tCYC6-tEWLW-tEWHW). 2. All timing is rated based on 20 to 80% of VDD1.
Data Sheet S15817EJ2V0DS
79
PD161623
(c) Common
Parameter Oscillation frequency Symbol fOSC1 fOSC2 fOSC3 Condition Internal oscillator, 240 line (NGO = 0) Internal oscillator, 220 line (NGO = 1) External oscillator, 240 line (NGO = 0), resistance for oscillator RL = 42 k MIN. 370 300 TYP.
Note1
MAX. 850 760
Unit kHz kHz kHz
535 490 536.2
Note5
5
Calibration setting time (frame frequency)
tcal1 (fFRAME01) tcal2 (fFRAME02)
Internal oscillator, 240 line (NGO = 0), Note2 Internal oscillator, 220 line (NGO = 1), Note2 Uncalibrated Calibrated Calibrated
Note3 Note4
29.7 (139.6) 36.7 (123.4) 40 54 56
69.1 (60) 69.1 (60) 60 60 60 535 490
162.4 (25.6) 181.6 (24.9) 95 66 64
s
(Hz)
s
(Hz) Hz Hz Hz kHz kHz ns ns ns
Frame frequency
fFRAME1 fFRAME2 fFRAME3
Input oscillation frequency
fOSCIN1 fOSCIN2
External oscillator, 240 line (NGO = 0) External oscillator, 220 line (NGO = 1) VDD2 or VDD1 to /RESET 100 100 /RESET to interface operation 100
Reset pulse width at power on Reset pulse width Reset time
tVR tRW tR
Notes 1. TYP. values are reference values when TA = 25C. 5 2. The relationship between the frame frequency and the calibration setting time is as follows. 1 fFRAME01 = tcal x 241 fFRAME02 = 1 tcal x 221
3. Measured at TA = -40 to +85C, after calibration at frame frequency = 60 Hz, TA = 25C exactly. 4. Measured at 5C, after calibration at frame frequency = 60 Hz exactly. 5. This value is a reference value in some measurement conditions. Note that be able to use and obtain after a real board's fully estimating.
80
Data Sheet S15817EJ2V0DS
PD161623
9. PD161623, 161641, and 161660 CONNECTION DIAGRAM EXAMPLE
Connection diagram examples for the PD161623, 161641, and 161660 are shown below.
1.7 V to VDD2
CPU
RESET D0 to D17 /WR (R,/W) /RD (E) /CS An
VDD
2.5 to 3.6 V
RESET D0 to D17 /WR (R,/W) /RD (E) /CS RS
VDD2
VCC1
VDD1 VS DCON VS
2.5 to 5.5 V
VDC DCON RGONP VCE VCD11 VCD12 VCD2 LPMP
RGONP VCOMR VCOM VCOUT1 VCE VCD11 VCD12 VCD2 LPMP
PD161660
VSS
PD161623
VO
VT
GND(0 V)
GCLK GSTB GOE1 GOE2 FBRSEL VSS
Y527 Y528
Y1 Y2
COMMON O1 O2
TFT-LCD Panel 176 x RGB x 240
PD161641
O240 SB VSS
Data Sheet S15817EJ2V0DS
OE2 OE1 STVR(STVL) CLK VT VEE VCC1
81
PD161623
10. EXAMPLE of PD161623 and CPU CONNECTION
Examples of PD161623 and CPU connection are shown below. In the example below, RS pin control in parallel interface mode is described for the case when the least significant bit of the address bus is being used.
(1) i80 series format
CPU
PD161623
(2) M68 series format
CPU
PD161623
VDD2 VDD /CS A0 D0 to D17 /RD /WR /RESET VSS VDD1 /CS RS D0 to D17 /RD /WR /RESET VSS VDD /CS A0 D0 to D17 R, /W E /RESET VSS
VDD2 VDD1 /CS RS D0 to D17 R, /W E /RESET VSS
82
Data Sheet S15817EJ2V0DS
PD161623
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S15817EJ2V0DS
83

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